SM59D03G2 Datasheet, PDF (54/67 Pages) SyncMOS Technologies,Inc – 8-Bits Micro-controller

12.1 EEI SFR description
SM59D03G2
8-Bits Micro-controller
8KB+ ISP Flash & 1KB RAM embedded
Mnemonic
KBLS
KBE
KBF
Description
EEI level Selector
register
EEI Input Enable
register
EEI Flag register
Direct
FDh
FEh
FFh
Bit 7
Bit 6 Bit 5 Bit 4
Keyboard interface
Bit 3
Bit 2
Bit 1
Bit 0
KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
RESET
00h
00h
00h
12.1.1 EEI level selector register
Mnemonic: KBLS
7
6
KBLS7 KBLS6
R/W R/W
5
KBLS5
R/W
4
KBLS4
R/W
3
KBLS3
R/W
2
KBLS2
R/W
1
KBLS1
R/W
Address: FDh
0 Reset
KBLS0 00h
R/W
KBLS7: EEI line 7 level selection bit
Cleared to enable a low level detection on Port line 7.
Set to enable a high level detection on Port line 7.
KBLS6: EEI line 6 level selection bit
Cleared to enable a low level detection on Port line 6.
Set to enable a high level detection on Port line 6.
KBLS5: EEI line 5 level selection bit
Cleared to enable a low level detection on Port line 5.
Set to enable a high level detection on Port line 5.
KBLS4: EEI line 4 level selection bit
Cleared to enable a low level detection on Port line 4.
Set to enable a high level detection on Port line 4.
KBLS3: EEI line 3 level selection bit
Cleared to enable a low level detection on Port line 3.
Set to enable a high level detection on Port line 3.
KBLS2: EEI line 2 level selection bit
Cleared to enable a low level detection on Port line 2.
Set to enable a high level detection on Port line 2.
KBLS1: EEI line 1 level selection bit
Cleared to enable a low level detection on Port line 1.
Set to enable a high level detection on Port line 1.
KBLS0: EEI line 0 level selection bit
Cleared to enable a low level detection on Port line 0.
Set to enable a high level detection on Port line 0.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M030
54
Ver.C SM59D03G2 07/2009