SM59D03G2 Datasheet, PDF (26/67 Pages) SyncMOS Technologies,Inc – 8-Bits Micro-controller

SM59D03G2
8-Bits Micro-controller
8KB+ ISP Flash & 1KB RAM embedded
7 Timer 2
Timer 2 is a 16-bit timer/counter which can operate either as a timer or an event counter. This is
selectable by bit C/T 2 in the SFR T2CON. It has three operating modes: capture, auto-reload (up
or down counting), and baud rate generator. The modes are selected by bits in T2CON as shown
below.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the timer function, the TL2 register is
incremented every machine cycle, thus one can think of it as counting machine cycles. Since a
machine cycle consists of a 12-clock period in 12T, the count rate is 1/12 of the oscillator clock
frequency. In 6T, it is 1/6.
In the counter function, the register is incremented in response to every 1-to-0 transition at its
corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of
every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the register during S3P1 of the cycle
following the one in which the transition was detected. Since it takes 2 machine cycles (24 clock
periods in 12T) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator
frequency in 12T mode or 1/12 in 6T mode. To ensure that a given level is sampled at least once
before it changes, it should be held for at least one full machine cycle.
RCLK+TCLK
0
0
1
X
Table 7-1 : Timer 2 Operating Modes
CP/ RL2
TR2
MODE
0
1
16-bit Auto-reload
1
1
16-bit Capture
X
1
Baud rate Generator
X
0
Off
7.1 Capture mode
In the capture mode, there are two options selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2
is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to
generate an interrupt. If EXEN2 = 1, Timer 2 still does the above, but with the added feature that a
1-to-0 transition at external input T2EX causes the current value in TH2 and TL2 to be captured into
RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON
to be set. The EXF2 bit, like TF2, can generate an interrupt.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M030
26
Ver.C SM59D03G2 07/2009