SM59D03G2 Datasheet, PDF (21/67 Pages) SyncMOS Technologies,Inc – 8-Bits Micro-controller

SM59D03G2
8-Bits Micro-controller
8KB+ ISP Flash & 1KB RAM embedded
6 Timer 0 and Timer 1
These timer and counter functions are presented in the same module. The “timer” or “counter”
function is selected by the control bits C/ T in SFR TMOD. Timer 0 and Timer 1 have four operation
modes, which are selected by bit-pairs (M1, M0) in SFR TMOD. Mode 0, 1, and 2 are the same for
both timer and counters. Mode 3 is different. The four operating modes are described below：
6.1 Mode 0
In this mode, the timer register is configured as a 13-bit register. Take Timer 1 as the example, as
the counter rolls over from all 1s to all 0s, it sets the Timer 1 interrupt flag TF1. The counter input is
enabled by the timer when TR1 = 1 and either GATE = 0 or INT1 = 1, here setting GATE = 1
allows the timer to be controlled by external input INT1, to facilitate pulse width measurements.
TR1 is a control bit in the SFR TCON and GATE is in TMOD.
The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1
are indeterminate and should be ignored. Setting the run flag (TR1) does not clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1. So substituting TR0, TF0 and INT 0 for the
corresponding Timer 1 signals in the last paragraph, we can know the operation of Mode 0 for
Timer 0. But there are two different GATE bits, one is for Timer 1(TMOD.7) and the other one is for
Timer 0 (TMOD.3).
OSC
/12
T1 pin
TR1
C/ T = 0
C/ T = 1
Control
TL1
(5 bits)
TH1
(8 bits)
TF1
Interrupt
GATE
INT1 ^pin
Fig. 6-1： Mode 0 operation for Timer 1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M030
21
Ver.C SM59D03G2 07/2009