SM59D03G2 Datasheet, PDF (53/67 Pages) SyncMOS Technologies,Inc – 8-Bits Micro-controller

SM59D03G2
8-Bits Micro-controller
8KB+ ISP Flash & 1KB RAM embedded
12 Expanded External Interrupt (EEI) interface
SM59D03G2 implements an EEI interface allowing the connection of an 8xn matrix keyboard. It is
based on 8 inputs with programmable interrupt capability for either high or low levels. These inputs
are available as an alternate function of P1 and allow to exit from idle and power-down modes given
in Section 14.
The EEI interfaces with the CPU core through 3 SFR: KBLS, the EEI Level Selection register, KBE,
the EEI Enable register, and KBF, the EEI Flag register.
The EEI inputs are considered as 8 independent interrupt sources sharing the same interrupt vector.
Figure 12-1 shows that each EEI input has the capability to detect a programmable level according
to KBLS.x bit value. Level detection is then reported in interrupt flags KBF.X that can be masked by
software using KBE.x bits. An interrupt enable bit (KBD in IE1) allows global enable or disable of
the keyboard interrupt as in Fig. 12-2.
This structure allows keyboard arrangements from 1xn to 8xn matrix, and allows usage of P1 inputs
for other purpose. P1 inputs allow exiting from the idle and power-down modes
Figure 12.1 EEI interface Block Diagram
EEI Interface
Interrupt Request
Figure 12.2 EEI input Circuitry
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M030
53
Ver.C SM59D03G2 07/2009