SM59D03G2 Datasheet, PDF (30/67 Pages) SyncMOS Technologies,Inc – 8-Bits Micro-controller

SM59D03G2
8-Bits Micro-controller
8KB+ ISP Flash & 1KB RAM embedded
Mnemonic: T2CON
7
6
5
4
3
2
TF2 EXF2 RCLK TCLK EXEN2 TR2
1
C/ T2
Address: C8h
0
Reset
CP/ RL2 ^00h
TF2: Timer 2 overflow flag is set by a Timer 2 overflow and must be cleared by
software. TF2 will not be set when either RCLK = 1 or TCLK = 1.
EXF2: Timer 2 external flag is set when either a capture or reload is caused by a
negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is
enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt
routine. EXF2 must be cleared by software. EXF2 does not cause an
interrupt in up/down counter mode (DCEN = 1).
RCLK: Receive clock enable. When set, causes the serial port to use Timer 2
overflow pluses for its receive clock in serial port Modes 1 and 3. RCLK =
0 causes Timer 1 overflows to be used for the receive clock.
TCLK: Transmit clock enable. When set, causes the serial port to use Timer 2
overflow pulses for it’s transmit clock in serial port Modes 1 and 3. TCLK =
0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2: Timer 2 external enable. When set, allows a capture or reload to occur as
a result of a negative transition on T2EX if Timer 2 is not being used to
clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2: Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/ T2 : Timer or counter select for Timer 2. C/ T2 = 0 for timer function. C/ T2 = 1
for external event counter (falling edge triggered).
CP/ RL2 : Capture/Reload select. CP/ RL2 = 1 causes captures to occur on negative
transitions at T2EX if EXEN2 = 1. CP/ RL2 = 0 causes automatic reloads
to occur when Timer 2 overflows or negative transitions occur at T2EX
when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and
the timer is forced to auto-reload on Timer 2 overflow.
Mnemonic: T2MOD
Address: C9h
7
6
5
4
3
2
1
0 Reset
-
-
-
-
-
-
T2OE DCEN x0h
T2OE: Timer 2 Output Enable bit.
DCEN: When set, this bit allows Timer 2 to be configured as an up/down counter.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M030
30
Ver.C SM59D03G2 07/2009