SM59D03G2 Datasheet, PDF (31/67 Pages) SyncMOS Technologies,Inc – 8-Bits Micro-controller

SM59D03G2
8-Bits Micro-controller
8KB+ ISP Flash & 1KB RAM embedded
8 Watchdog timer
The watchdog timer is an 8-bit counter that is incremented once every WDTCLK clock cycle. After
an external reset, the watchdog timer is disabled and all registers are set to zero.
When SM59D03G2 is reset, it will read internal setting for the bit WDTEN.When the WDTEN is
selected ,the watchdog function will enable. The WDTM[2:0] is control WDTCLK. User can select
WDTEN on the writer.
Table 8-1 Watchdog Timer Overflow Period：
WDTM[2:0]
000
OverFlow Period 1.58ms
001
3.15ms
010
011
100
101
110
111
6.30ms 12.60ms 25.12ms 50.41ms 100.82ms 201.65ms
The watchdog timer will reset the system after 256 WDTCLK is reached. Once the watchdog is
started it cannot be stopped. To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC.
After WDTE set to 1, the 16-bit counter starts to count. It will generate a reset signal when
overflows. The WDTE bit will be cleared to 0 automatically when SM59D04G2 been reset, either
hardware reset or WDT reset
To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This
will clear the content of the 16-bit counter and let the counter re-start to count from the beginning.
The SFR WDTK[7:0] must be set first. The first value set to it is 1Eh, then the next value is E1h.
Mnemonic Description
WDTC
WDTK
Watchdog timer
control register
Watchdog timer
refresh key
Direct Bit 7
8Eh WDTE
8Fh
Bit 6 Bit 5 Bit 4
Watchdog Timer
-
CLEAR
-
Bit 3
-
WDTK[7:0]
Bit 2 Bit 1 Bit 0 RESET
WDTM2 WDTM1 WDTM0
00H
00H
Mnemonic: WDTC
7
6
5
4
WDTE
-
CLEAR
-
Address: 8Eh
3
2
1
0
Reset
-
WDTM2 WDTM1 WDTM0 00H
WDTM[2:0]:
WDTE:
CLEAR
Watchdog timer over flow period setting.
Watchdog timer Enable.
WDTE=0：Disable WDT function either the WDTEN was setting on
the Writer。
WDTE=1：Enable WDT function when the WDTEN was setting on
the Writer。
This bit will be cleared to 0 automatically when MCU been reset,
either hardware reset or WDT reset。
Setting this bit the Watchdog timer counter clear and re-start to count
from the Beginning。
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M030
31
Ver.C SM59D03G2 07/2009