UM0434 Datasheet, PDF (90/390 Pages) STMicroelectronics – The primary objective of this user’s manual is to describe

UM0434
Register model
Table 70. TLB0CFG field descriptions (continued)
Bits Name
Description
Page size availability.
49
AVAIL
0
50–51
—
Reserved, should be cleared.
Number of entries.
52–63 NENTRY
0 TLB0 contains 0 entries.
TLB configuration register 1 (TLB1CFG)
TLB1CFG, shown in Table 71, provides information on the TLB1 configuration.
Table 71. TLB configuration register 1 (TLB1CFG)
32
39 40
43 44
47
Field
ASSOC
MINSIZE
MAXSIZE
48
IPROT
Reset 0010_0000
0001
1001
1
R/W
Read only
SPR
SPR 689
The TLB1CFG fields are described in Table 72.
49
AVAIL
1
50 51 52
63
—
NENTRY
00
0000_0010_0000
Table 72. TLB1CFG field descriptions
Bits Name
Description
Associativity.
32–39 ASSOC
0x10 Indicates that TLB1 associativity is 16
Minimum page size.
40–43 MINSIZE
0x1 Smallest page size is 4 Kbytes.
Maximum page size.
44–47 MAXSIZE
0x9 Largest page size is 256 Mbytes.
Invalidate protect capability.
48 IPROT
1 Invalidate protect capability is supported in TLB1.
Page size availability.
49 AVAIL
1 All page sizes between MINSIZE and MAXSIZE are supported.
50–51 — Reserved, should be cleared.
Number of entries.
52–63 NENTRY
0x010 TLB1 contains 16 entries.
4.16.4
MMU assist registers (MAS0–MAS4, MAS6)
The e200z3 uses six special purpose registers (MAS0–MAS4, and MAS6) for reading,
writing, and searching the TLBs. The MAS registers can be read or written using the mfspr
and mtspr instructions. The e200z3 does not implement the MAS5 register, which is
present in other Book E designs, because the tlbsx instruction only searches based on a
single SPID value.
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