UM0434 Datasheet, PDF (192/390 Pages) STMicroelectronics – The primary objective of this user’s manual is to describe

UM0434
Memory management unit
Table 150. TLB maintenance programming model
Features
Description
tlbre
TLB Read Entry instruction
tlbwe
TLB
Instructions
tlbsx rA, rB
tlbivax rA, rB
tlbsync
PID0
TLB Write Entry instruction
TLB Search for Entry instruction
TLB Invalidate Entries instruction
TLB Synchronize Invalidations with other masters’
instruction (privileged no-op on the e200z3)
Process ID register
MMUCSR0
MMU control and status register
Registers
MMUCFG
TLB0CFG–TLB1CFG
MMU configuration register
TLB configuration registers
MAS0–MAS4, MAS6
MMU assist registers. Note: e200z3 does not
implement MAS5.
DEAR
Data exception address register
Instruction TLB miss
exception
Causes instruction TLB error interrupt
Interrupts
Data TLB miss exception Causes data TLB error interrupt
Instruction permission
violation exception
Causes ISI interrupt
Data permission violation
exception
Causes DSI interrupt
Section/page
Chapter 7.4 on
page 200
Chapter 7.4 on
page 200
Chapter 7.4 on
page 200
Chapter 7.4 on
page 200
Chapter 7.4 on
page 200
Chapter 4.4.2
on page 45
Chapter 4.16.1
on page 88
Chapter 4.16.2
on page 89
Chapter 4.16.3
on page 90
Chapter 4.16.4
on page 91
Chapter on
page 57
Chapter 6.6.15
on page 179
Chapter 6.6.14
on page 179
Chapter 6.6.4
on page 172
Chapter 6.6.3
on page 171
Other hardware assistance features for maintenance of the TLB on the e200z3 are
described in Chapter : MAS register updates on page 205.”
7.2
Effective to real address translation
This section describes the general principles that guide the PowerPC Book E definition for
memory management and further describes the structure for MMUs defined by the
Freescale Book E implementation standard (EIS) and the e200z3 MMU.
Figure 7 shows the high-level translation flow, showing that because the smallest page size
supported by the e200z3 core complex is 4 Kbytes, the 12 lsbs always index within the page
and are untranslated.
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