UM0434 Datasheet, PDF (314/390 Pages) STMicroelectronics – The primary objective of this user’s manual is to describe

UM0434
Debug support
The OnCE decoder receives as input the 10-bit command from the OCMD and the status
signals from the processor, and generates all the strobes required for reading and writing
the selected OnCE registers.
Single-stepping of instructions is performed by placing the CPU in debug mode, scanning
appropriate information into the CPUSCR, and setting the GO bit (with the EX bit cleared)
with the RS field indicating either the CPUSCR or no register selected. After executing a
single instruction, the CPU re-enters debug mode and awaits further commands. During
single-stepping, exception conditions may occur if not properly masked by debug firmware
(interrupts, machine checks, bus error conditions, and so on) and may prevent the desired
instruction from being successfully executed. The OSR[ERR] bit is set to indicate this
condition. In these cases, values in the CPUSCR correspond to the first instruction of the
exception handler.
Additionally, while single-stepping, to prevent debug events from generating debug
interrupts, DBCR0[EDM] is internally forced to 1. Also, during a debug session, DBSR and
DBCNT are frozen from updates due to debug events regardless of DBCR0[EDM]. They
may still be modified during a debug session through a single-stepped mtspr instruction if
DBCR0[EDM] is cleared, or through OnCE access if DBCR0[EDM] is set.
OnCE control register (OCR)
The OCR, shown in Table 203, forces the core into debug mode and enables/disables
sections of the OnCE control logic. It also provides control over the MMU during a debug
session. (See Chapter 11.7: MMU and cache operation during debug on page 327.”) The
control bits are read/write. These bits are effective only while OnCE is enabled (jd_en_once
set).
Table 203. OnCE control register fields
0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 28 29 30 31
Field — I_DMDIS — I_DVLE I_DI I_DM I_DE DMDIS — DW DI DM DG DE — WKUP FDB DR
Reset
0x0000_0000 on m_por, j_trst_b, or entering test-logic-reset state
Table 204 describes OnCE control register fields.
Table 204. OnCE control register bit definitions
Bits Name
Description
0–7
— Reserved, should be cleared.
Instruction side debug MMU disable control bit. May be used to control whether the MMU is
enabled or disabled during a debug session for instruction accesses.
0MMU not disabled for debug sessions. The MMU functions normally.
8 I_DMDIS ^{1MMU disabled for debug sessions. For instruction accesses, no address translation is}
performed (1:1 address mapping) and the TLB IME bits are taken from the OCR bits I_DI,
I_DM, and I_DE. The SX and UX access permission control bits are set, allowing full access.
When disabled, no TLB miss or TLB exceptions are generated for instruction accesses.
External access errors can still occur.
9–10
— Reserved, should be cleared.
11
I_DVLE
Instruction side debug TLB VLE attribute bit. Provides the VLE attribute bit for when the MMU is
disabled during a debug session.
315/391