UM0434 Datasheet, PDF (26/390 Pages) STMicroelectronics – The primary objective of this user’s manual is to describe

UM0434
e200z3 core complex overview
Figure 2. e200z3 programmer’s model
General-Purpose Registers
User-Level Registers
Instruction-Accessible Registers
User General SPR (Read/Write)
0
31 32
63
(upper) GPR0¹ (lower)
GPR1
GPR2
····
General-
purpose
registers
GPR31
L1 Cache (Read-Only)
spr 515 L1CFG0³
L1 cache
configuration
register 0
0
31 32
63
CR
Condition register
spr 9 CTR
Count register
spr 8
LR
Link register
spr 1 XER
spr 512 SPEFSCR³
ACC³
Integer exception
register
SP/embedded FP
status/control register
Accumulator
32
63
spr 256 USPRG0²
User SPR
general 0
General SPRs (Read-Only)
spr 260
spr 261
spr 262
spr 263
SPRG4
SPRG5
SPRG6
SPRG7
SPR general
registers 4–7
Time-Base Registers (Read-Only)
spr 268
spr 269
TBL
TBU
Time base
lower/upper
Supervisor-Level Registers
Interrupt Registers
Configuration Registers
32
63
spr 63 IVPR
Interrupt vector
prefix register
spr 26
spr 27
SRR0
SRR1
Save/restore
registers 0/1
spr 58 CSRR0
spr 59 CSRR1
Critical SRR 0/1
spr 574 DSRR0³
spr 575 DSRR1³
spr 62
spr 572
ESR
MCSR ³
spr 61 DEAR
Debug interrupt
SRR 0/1
Exception syndrome
register
Machine check
syndrome register
Data exception
address register
Debug Registers
spr 308
spr 309
spr 310
spr 561
DBCR0
DBCR1
DBCR2
DBCR3
Debug control
registers 0–3
spr 304 DBSR
spr 562 DBCNT ⁵
Debug status register
Debug count register
spr 312
spr 313
spr 314
spr 315
IAC1
IAC2
IAC3
IAC4
Instruction address
compare
registers 1–4
spr 316
spr 317
DAC1
DAC2
Data address
compare
registers 1 and 2
32
63
spr 400 IVOR0
spr 401 IVOR1
····
Interrupt vector offset
registers 0–15⁴
spr 415 IVOR15
spr 528
spr 529
spr 530
IVOR32 ³
IVOR33 ³
IVOR34 ³
Interrupt vector offset
registers 32–34
32
63
MSR
Machine state register
spr 1023 SVR³
System version
register
spr 286 PIR
Processor ID register
spr 287 PVR
Processor version
register
Timer/Decrementer Registers
MMU Control and Status (Read/Write)
spr 1012 MMUCSR0³
spr 624
spr 625
spr 626
spr 627
spr 628
spr 630
MAS0 ³
MAS1 ³
MAS2 ³
MAS3 ³
MAS4 ³
MAS6 ³
MMU control and status
register 0
MMU assist registers
0–4 and 6
spr 22 DEC
spr 54 DECAR
spr 284
spr 285
TBL
TBU
Decrementer
Decrementer
auto-reload register
Time base
lower/upper
spr 340 TCR
Timer control register
spr 336 TSR
Timer status register
Miscellaneous Registers
spr 48 PID0
Process ID
register 0
MMU Control and Status (Read Only)
spr 1015 MMUCFG³ MMU configuration
spr 688 TLB0CFG³
spr 689 TLB1CFG^{3 TLB configuration 0/1}
spr 1008
spr 1009
HID0 ³
HID1 ³
spr 1013 BUCSR⁵
spr 272–279 SPRG0–7
Hardware
implementation
dependent 0–1
Branch control and
status register
General SPRs 0–7
Context Control (Read/Write)
Parallel Signature Unit Registers⁵
spr 560 CTXCR⁵
Context control
register
dcr 272
dcr 273
dcr 274
dcr 275
dcr 276
dcr 277
dcr 278
PSCR
PSSR
PSHR
PSLR
PSCTR
PSUHR
PSULR
PS control
PS status
PS high
PS low
PS counter
PS update high
PS update low
1. The 64-bit registers are accessed by the SPE as separate 32-bit registers by SPE instructions. Only SPE
vector instructions can access the upper word.
2. USPRG0 is a separate physical register from SPRG0.
3. EIS specific registers not part of the Book E architecture.
4. IVOR9 (handles auxiliary processor unavailable interupt) is defined by the EIS but not supported by the
e200z3.
5. e200z3 specific registers may not be supported by other PowerPC processors.
3.3
Instruction set
The e200z3 implements the following instructions:
● The Book E instruction set for 32-bit implementations. This is composed primarily of
the user-level instructions defined by the PowerPC user instruction set architecture
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