UM0434 Datasheet, PDF (190/390 Pages) STMicroelectronics – The primary objective of this user’s manual is to describe

UM0434
Interrupts and exceptions
6.8.2
automatically when a debug interrupt is taken to mask further recognition of conditions
causing those exceptions. Chapter 11: Debug support,” gives details on individual
control of debug exceptions.
● The floating-point unavailable exception can be prevented by setting MSR[FP]
(although the e200z3 generates an unimplemented instruction exception instead).
Returning from an interrupt handler
The Return from Interrupt (rfi), Return from Critical Interrupt (rfci) and Return from Debug
Interrupt (rfdi) instructions perform context synchronization by allowing instructions issued
earlier to complete before returning to the interrupted process. In general, execution of rfi,
rfci, or rfdi ensures the following:
● All previous instructions have completed to a point where they can no longer cause an
exception. This includes post-execute type exceptions.
● Previous instructions complete execution in the context (privilege and protection) under
which they were issued.
● The rfi copies SRR1 bits back into the MSR.
● The rfci copies CSRR1 bits back into the MSR.
● The rfdi copies DSRR1 bits back into the MSR.
● Instructions fetched after this execution in the context established by this instruction.
● Program execution resumes at the instruction indicated by SRR0 for rfi, CSRR0 for rfci
or DSRR0 for rfdi.
Note that the rfi may be subject to a return type debug exception and that rfci may be
subject to a critical return type debug exception. For a complete description of context
synchronization, refer to the EREF.
6.9
Process switching
The following instructions are useful for restoring proper context during process switching:
● msync orders the effects of data memory instruction execution. All instructions
previously initiated appear to have completed before the msync instruction completes,
and no subsequent instructions appear to be initiated until the msync instruction
completes.
● isync waits for all previous instructions to complete and then discards any fetched
instructions, causing subsequent instructions to be fetched (or refetched) from memory
and to execute in the context (privilege, translation, and protection) established by the
previous instructions.
● stwcx. clears any outstanding reservations, ensuring that a load and reserve
instruction in an old process is not paired with a store conditional instruction in a new
one.
191/391