UM0434 Datasheet, PDF (187/390 Pages) STMicroelectronics – The primary objective of this user’s manual is to describe

Interrupts and exceptions
UM0434
Table 148. e200z3 exception priorities (continued)
Priority
Exception
Cause
IVOR
Debug: BRT
Debug: Trap
Debug: RET
Debug: CRET
Attempted execution of a taken branch instruction
Condition specified in tw or twi instruction met.
Attempted execution of a rfi instruction
15
Attempted execution of an rfci instruction
Exceptions require corresponding debug event enabled,
MSR[DE]=1, and DBCR0[IDM]=1.
Program: trap
Condition specified in tw or twi instruction met and not a
debug trap exception
15
System call
Execution of the system call (sc, se_sc) instruction.
8
SPE floating-point
data
NaN, infinity, or denormalized data detected as input or
output, or underflow, overflow, divide by zero, or invalid
operation in the SPE APU.
33
SPE round
Inexact result
34
Alignment
lmw, stmw, lwarx, or stwcx. Not word aligned. dcbz with
cache disabled or not present
5
Debug with concurrent DTLB or data storage interrupt.
DBSR[IDE] also set.
Debug with
Data address compare linked with instruction address
concurrent DTLB or compare
data storage
interrupt:
DAC/IAC linked⁽²⁾
DAC unlinked²
Data address compare unlinked
15
Note: Exceptions require corresponding debug event
enabled, MSR[DE]=1, and DBCR0[IDM]=1. In this case, the
debug exception is considered imprecise and DBSR[IDE] is
set. Saved PC points to the load or store instruction causing
the DAC event.
Data TLB error
Data translation lookup miss in the TLB.
13
Data storage
Debug: IRPT
Debug: CIRPT
Access control.
Byte ordering due to misaligned access across page
boundary to pages with mismatched E bits.
2
Precise external termination error (p_tea_b assertion and
precise recognition) and MSR[EE]=1
Interrupt taken (non-critical)
Critical interrupt taken (critical only)
15
Note: Exceptions require corresponding debug event
enabled, MSR[DE]=1 and DBCR0[IDM]=1.
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