UM0434 Datasheet, PDF (79/390 Pages) STMicroelectronics – The primary objective of this user’s manual is to describe

Register model
UM0434
Table 56. DBCR3 field descriptions (continued)
Bits Name
Description
Instruction address compare 3 debug event count 1 enable.
37 IAC3C1 0 Counting IAC3 debug events by counter 1 is disabled.
1 Counting IAC3 debug events by counter 1 is enabled.
Instruction address compare 4 debug event count 1 enable.
38 IAC4C1 0 Counting IAC4 debug events by counter 1 is disabled.
1 Counting IAC4 debug events by counter 1 is enabled.
Data address compare 1 read debug event count 1 enable⁽¹⁾.
39 DAC1RC1 0 Counting DAC1R debug events by counter 1 is disabled.
1 Counting DAC1R debug events by counter 1 is enabled.
Data address compare 1 write debug event count 1 enable ⁽¹⁾.
40 DAC1WC1 0 Counting DAC1W debug events by counter 1 is disabled.
1 Counting DAC1W debug events by counter 1 is enabled.
Data address compare 2 read debug event count 1 enable ⁽¹⁾.
41 DAC2RC1 0 Counting DAC2R debug events by counter 1 is disabled.
1 Counting DAC2R debug events by counter 1 is enabled.
Data address compare 2 write debug event count 1 enable ⁽¹⁾.
42 DAC2WC1 0 Counting DAC2W debug events by counter 1 is disabled.
1 Counting DAC2W debug events by counter 1 is enabled.
Interrupt taken debug event count 1 enable.
43 IRPTC1 0 Counting IRPT debug events by counter 1 is disabled.
1 Counting IRPT debug events by counter 1 is enabled.
Return debug event count 1 enable.
44 RETC1 0 Counting RET debug events by counter 1 is disabled.
1 Counting RET debug events by counter 1 is enabled.
External debug event 1 count 2 enable.
45 DEVT1C2 0 Counting DEVT1 debug events by counter 2 is disabled.
1 Counting DEVT1 debug events by counter 2 is enabled.
External debug event 2 count 2 enable.
46 DEVT2C2 0 Counting DEVT2 debug events by counter 2 is disabled.
1 Counting DEVT2 debug events by counter 2 is enabled.
Instruction complete debug event count 2 enable.
0 Counting ICMP debug events by counter 2 is disabled.
47 ICMPC2
1 Counting ICMP debug events by counter 2 is enabled.
ICMP events are masked by MSR[DE] = 0 when operating in internal debug mode.
Instruction address compare 1 debug event count 2 enable.
48 IAC1C2 0 Counting IAC1 debug events by counter 2 is disabled.
1 Counting IAC1 debug events by counter 2 is enabled.
Instruction address compare2 debug event count 2 enable.
49 IAC2C2 0 Counting IAC2 debug events by counter 2 is disabled.
1 Counting IAC2 debug events by counter 2 is enabled.
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