TS5070 Datasheet, PDF (9/32 Pages) STMicroelectronics – PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION

TS5070 - TS5071
CONTROL REGISTER INSTRUCTION
The first byte of a READ or WRITE instruction to
the Control Register is as shown in table 1. The
second byte functions are detailed in table 2.
MASTER CLOCK FREQUENCY SELECTION
A Master clock must be provided to COMBO IIG
for operation of the filter and coding/decoding
functions. The MCLK frequency must be either
512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or
4.096 MHz and must be synchronous with BCLK.
Bits F1 and F0 (see table 2) must be set during
initialization to select the correct internal divider.
CODING LAW SELECTION
Bits ”MA” and ”IA” in table 2 permit the selection
of µ255 coding or A-law coding with or without
even-bit inversion.
Table 2: Control Register Byte 2 Functions
ANALOG LOOPBACK
Analog Loopback mode is entered by setting the
”AL” and ”DL” bits in the Control Register as shown
in table 2. In the analog loopback mode, the Trans-
mit input VF_XI is isolated from the input pin and in-
ternally connected to the VFRO output, forming a
loop from the Receive PCM Register back to the
Transmit PCM Register. The VFRO pin remains ac-
tive, and the programmed settings of the Transmit
and Receive gains remain unchanged, thus care
must be taken to ensure that overload levels are
not exceeded anywhere in the loop.
Hybrid balancing must be disabled for meaning
ful analog loopback Function.
DIGITAL LOOPBACK
Digital Loopback mode is entered by setting the
”DL” bit in the Control Register as shown in table 2.
Bit Number
7
6
5
4
3
2
1
0
Fun ction
F1
F0
MA
IA
DN
DL
AL
PP
0
0
0
1
1
0
1
1
0
X
1
0
1
1
MCLK = 512 kHz
MCLK = 1. 536 or 1. 544 MHz
MCLK = 2. 048 MHz ^*
MCLK = 4. 096 MHz
Select µ. 255 Law ^*
A–law, Including Even Bit Inversion
A–Law, No Even Bit Inversion
0
1
0
0
1
X
0
1
Delayed Data Timing
Non–delayed Data Timing ^*
Normal Operation ^*
Digital Loopback
Analog Loopback
0
Power Amp Enabled in PDN
1
Power Amp Disabled in PDN ^*
(*) State at power-on initialization (bit 4 = 0)
Table 3: Coding Law Conventions.
m255 Law
MSB LSB
True A-law with
even bit inversion
MSB LSB
A-law without
even bit inversion
MSB LSB
VIN = +Full Scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1
V_IN = 0V
111111111101010110000000
011111110101010100000000
V_IN = -Full Scale 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1
Note: The MSB is always the first PCM bit shifted in or out of COMBO IIG.
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