TS5070 Datasheet, PDF (20/32 Pages) STMicroelectronics – PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION

TS5070 - TS5071
Figure 6: Delayed Data Timing (short frame mode)
SERIAL CONTROL PORT TIMING
Symbol
f_CCLK
t_WCH
t_WCL
t_RC
t_FC
t_HCS
t_HSC
t_SSC
t_SSCO
t_SDC
t_HCD
t_DCD
tDSD
t_DDZ
Parameter
Frequency of CCLK
Period of CCLK High (measured from V_IH to V_IH)
Period of CCLK Low (measured from V_IL to V_IL)
Rise Time of CCLK (measured from V_IL to V_IH)
Fall Time of CCLK (measured from V_IH to V_IL)
Hold Time, CCLK Low to CS Low (CCLK1)
Hold Time, CCLK Low to CS High (CCLK8)
Setup Time, CS Transition to CCLK Low
Setup Time, CS Transition to CCLK High (to insure CO is not
enabled for single byte)
Setup Time, CI (CI/O) Data in to CCLK low
Hold Time, CCLK Low to CI (CI/O) Invalid
Delay Time, CCLK High to CO (CI/O) Data Out Valid
(load = 100 pF plus 2 LSTTL loads)
Delay Time, CS Low to CO (CI/O) Valid
(applies only if separate CS used for byte 2)
Delay Time, CS or CCLK9 High to CO (CI/O) High Impedance
(applies to earlier of CS high or CCLK9 high)
INTERFACE LATCH TIMING
Symbol
t_SLC
tHCL
tDCL
Parameter
Setup Time, I_L Valid to CCLK 8 of Byte 1 Low. I_L as Input
Hold Time, IL Valid from CCLK 8 of Byte 1 Low. IL as Input
Delay Time, CCLK 8 of Byte 2 Low to IL. CL = 50 pF. IL as Output
MASTER RESET PIN
Symbol
Parameter
t_WMR Duration of Master Reset High
Min.
160
160
10
100
70
50
50
50
15
Min.
100
50
Min.
1
Typ.
Max.
2.048
50
50
80
80
80
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Typ. Max. Unit
ns
ns
200
ns
Typ.
Max.
Unit
µs
20/32