TS5070 Datasheet, PDF (19/32 Pages) STMicroelectronics – PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION

TS5070 - TS5071
TIMING SPECIFICATIONS (continued)
PCM INTERFACE TIMING
Symbol
f_BCLK
t_WBH
t_WBL
t_RB
t_FB
t_HBF
t_SFB
t_DBD
t_DBZ
t_DBT
tZBT
t_DFD
t_SDB
t_HBD
Parameter
Frequency of BCLK (may vary from 64KHz to 4.096MHz in 8KHz
increments, TS5070 only)
Period of BCLK High (measured from V_IH to V_IH)
Period of BCLK Low (measured from V_IL to V_IL)
Rise Time of BCLK (measured from V_IL to V_IH)
Fall Time of BCLK (measured from V_IH to V_IL)
Hold Time, BCLK Low to FS_X/R High or Low
Setup Time FS_X/R High to BCLK Low
Delay Time, BCLK High to Data Valid (load = 100pF plus 2 LSTTL
loads)
Delay Time from BCLK8 Low to Dx Disabled (if FSx already low);
FSx Low to Dx Disabled (if BCLK8 low);
BCLK9 High to Dx Disabled (if FSx still high)
Delay Time from BCLK and FSx Both High to TSx Low (Load = 100pF
plus 2 LSTTL loads)
Delay Time from BCLK8 low to TSx Disabled (if FSx already low);
FSx Low to TSx Disabled
(if BCLK8 low);
BCLK9 High to TSx Disabled
(if FSx still high);
Delay Time, FSx High to Data Valid (load = 100pF plus 2 LSTTL
loads, applies if FSx rises later than BCLK rising edge in non-
delayed data mode only)
Setup Time, D_R 0/1 Valid to BCLK Low
Hold Time, BCLK Low to DR0/1 Invalid
Min.
64
80
80
30
30
15
15
30
20
Typ.
Max.
4096
30
30
80
80
60
60
80
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5: Non Delayed Data Timing (short frame mode)
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