TS5070 Datasheet, PDF (7/32 Pages) STMicroelectronics – PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION

POWER-DOWN STATE
Following a period of activity in the powered-up
state the power-down state may be re-entered by
writing any of the control instructions into the serial
control port with the ”P” bit set to ”1” It is recom-
mended that the chip be powered down before writ-
ing any additional instructions. In the power-down
state, all non-essential circuitry is de-activated and
the D_X0 and D_X1 outputs are in the high impedance
TRI-STATE condition.
The coefficients stored in the Hybrid Balance circuit
and the Gain Control registers, the data in the LDR
and ILR, and all control bits remain unchanged in
the power-down state unless changed by writing
new data via the serial control port, which remains
operational. The outputs of the Interface Latches
also remain active, maintaining the ability to moni-
tor and control a SLIC.
TRANSMIT FILTER AND ENCODER
The Transmit section input, VFXI, is a high imped-
ance summing input which is used as the differenc-
ing point for the internal hybrid balancecancellation
signal. No external components are needed to set
the gain. Following this circuit is a programmable
gain/attenuationamplifier which is controlled by the
contents of the Transmit Gain Register (see Pro-
grammable Functions section). An active prefilter
then precedes the 3rd order high-pass and 5th or-
der low-pass switched capacitor filters. The A/D
converter has a compressingcharacteristicaccord-
ing to the standard CCITT A or µ255 coding laws,
which must be selected by a controlinstructiondur-
ing initialization (see table 1 and 2). A precision on-
chip voltage reference ensures accurate and highly
stable transmission levels. Any offset voltage aris-
ing in the gain-set amplifier, the filters or the com-
parator is cancelled by an internal auto-zero circuit.
Each encode cycle begins immediately following
the assigned Transmit time-slot. The total signal
delay referenced to the start of the time-slot is ap-
proximately 165 µs (due to the Transmit Filter)
plus 125 µs (due to encoding delay), which totals
290 µs. Data is shifted out on D_X0 or D_X1 during
the selected time slot on eight rising edges of
BCLK.
DECODER AND RECEIVE FILTER
PCM data is shifted into the Decoder’s Receive
PCM Register via the D_R0 or D_R1 pin during the se-
lected time-slot on the 8 fallingedges of BCLK. The
Decoder consists of an expanding DAC with either
A or µ255 law decoding characteristic, which is se-
lected by the same control instructionused to select
the Encode law during initialization. Following the
Decoder is a 5th order low-pass switched capacitor
filter with integral Sin x/x correction for the 8 kHz
sample and hold. A programmable gain amplifier,
which must be set by writing to the Receive Gain
TS5070 - TS5071
Register,is included,and finally a Post-Filter/Power
Amplifier capable of driving a 300 Ω load to ± 3.5
V, a 600 Ω load to ± 3.8 V or 15 kΩ load to ± 4.0 V
at peak overload.
A decode cycle begins immediately after each re-
ceive time-slot, and 10 µs later the Decoder DAC
output is updated. The total signal delay is 10 µs
plus 120 µs (filter delay) plus 62.5 µs (1/2 frame)
which gives approximately 190 µs.
PCM INTERFACE
The FSX and FSR frame sync inputs determine the
beginning of the 8-bit transmit and receive time-
slots respectively. They may have any duration
from a single cycle of BCLK to one MCLK period
LOW. Two different relationships may be estab-
lished betweenthe framesync inputs and theactual
time-slots on the PCM busses by setting bit 3 in the
Control Register (see table 2). Non delayed data
mode is similar to long-frame timing on the
ETC5050/60 series of devices : time-slots being
nominally coincident with the rising edge of the ap-
propriate FS input. The alternative is to use De-
layed Data mode which is similar to short-frame
sync timing, in which each FS input must be high
at least a half-cycle of BCLK earlier than the time-
slot.
The Time-Slot Assignment circuit on the device can
only be used with Delayed Data timing. When using
Time-Slot Assignment, the beginning of the first
time-slot in a frame is identified by the appropriate
FS input. The actual transmit and receive time-slots
are then determined by the internal Time-Slot As-
signment counters. Transmit and Receive frames
and time-slots may be skewed from each other by
any number of BCLK cycles.
During each assigned transmit time-slot, the se-
lected D_X0/1 output shifts data out from the PCM
register on the rising edges of BCLK. TS_X0 (or
TSX1 as appropriate) also pulls low for the first 7
1/2 bit times of the time-slot to control the TRI-
STATE Enable of a backplane line driver. Serial
PCM data is shifted into the selected D_R0/1 input
during each assigned Receive time slot on the
falling edges of BCLK. DX0 or DX1 and DR0 or
DR1 are selectable on the TS5070 only.
SERIAL CONTROL PORT
Control information and data are written into or
readback from COMBO IIG via the serial control
port consistingof the controlclock CCLK ; the serial
data input/ou tput CI/O (or separate input CI, and
output CO on the TS5070 only) ; and the Chip Se-
lect input CS. All control instructions require 2
bytes,as listed in table 1, with the exceptionof a sin-
gle byte power-up/down command. The byte 1 bits
are used as follows: bit 7 specifies power-up or
power-down; bits 6, 5, 4 and 3 specify the register
address; bit 2 specifies whether the instructions is
read or write; bit 1 specifies a one or two byte in-
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