TS5070 Datasheet, PDF (2/32 Pages) STMicroelectronics – PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION

TS5070 - TS5071
TS5070 PIN FUNCTIONALITY (PLCC28)
No.
Name
Function
1
GND
Ground Input (+0V)
2
VF_R0
Analog Output
3
V_SS
Supply Input (-5V)
4
NC
Not Connected
5
NC
Not Connected
6
IL3
Digital Input or Output defined by LDR register content
7
IL2
Digital Input or Output defined by LDR register content
8
FS_R
Digital input
9
D_R1
Digital input sampled by BCLK falling edge
10
D_R0
Digital input sampled by BCLK falling edge
11
CO
Digital output (shifted out on CCLK rising edge)
12
CI
Digital input (sampled on CCLK falling edge)
13
CCLK
Digital input (clock)
14
CS
Digital input (chip select for CI/CO)
15
MR
Digital Input
16
BCLK
Digital input (clock)
17
MCLK
Digital input
18
D_X0
Digital output clocked by BCLK rising edge
19
D_X1
Digital output clocked by BCLK rising edge
20
TS_X0
Open drain output (pulled low by active DX0 time slot)
21
TS_X1
Open drain output (pulled low by active DX1 time slot)
22
FS_X
Digital input
23
IL5
Digital input or output defined by LDR register content
24
IL4
Digital input or output defined by LDR register content
25
IL1
Digital input or output defined by LDR register content
26
IL0
Digital input or output defined by LDR register content
27
V_CC
Supply input (+5V)
28
VF_XI
Analog input
TS5070 FUNCTIONAL DIAGRAM
VFXI
VCC=+5V
VSS=-5V
ENCODER
AZ
2/32
VFRO
GND
IL5
IL4
IL3
IL2
IL1
IL0
TX GAIN
HYBRID
BALANCE
FILTER
HYBAL 1
HYBAL 2
HYBAL 3
TS5070/71
TX TIME SLOT
Vref
CTL REG.
TX
REGISTER
TIME-SLOT
ASSIGNMENT
RX TIME SLOT
RX
REGISTER
RX GAIN
INTERFACE
LATCHES
LATCH DIR
LATCH CONT.
DECODER
CONTROL
INTERFACE
D94TL135
DX0
DX1
TSX0
TSX1
FSX
BCLK
FSR
DR0
DR1
MCLK
MR
CS
CCLK
CO
CI