TS5070 Datasheet, PDF (18/32 Pages) STMicroelectronics – PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION

TS5070 - TS5071
ELECTRICAL OPERATING CHARACTERISTICS (continued)
POWER DISSIPATION
Symbol
ICC0
-ISS0
ICC1
-ISS1
ICC2
-ISS2
Parameter
Power Down Current (CCLK, CI/O, CI = 0.4V, CS = 2.4V)
Interface Latches set as Outputs with no load
All over Inputs active, Power Amp Disabled
Power Down Current (as above)
Power Up Current (CCLK, CI/O, CI = 0.4V, CS = 2.4V)
No Load on Power Amp
Interface Latches set as Outputs with no Load
Power Up Current (as above)
Power Down Current with Power Amp Enabled
Power Down Current with Power Amp Enabled
Min. Typ. Max. Unit
0.3
1.5
mA
0.1
0.3
mA
7
11
mA
7
11
mA
2
4
mA
2
4
mA
TIMING SPECIFICATIONS
Unless otherwisenoted,limits in BOLDcharactersare
guaranteed for VCC = + 5 V ± 5 %; VSS = -5V ± 5 %.
TA = -40 °C to 85 °C by correlation with 100 % elec-
trical testing at T_A = 25 °C. All other limits are as-
sured by correlation with other production tests
and/or product design and characterization. All sig-
nals referenced to GND. Typicals specified at
VCC = + 5 V, VSS = -5 V, TA = 25 °C. All timing pa-
rametersaremeasuredatV_OH =2.0V andV_OL = 0.7 V.
See Definitions and Timing Conventions section
for test methods information.
MASTER CLOCK TIMING
Symbol
fMCLK
Parameter
Frequency of MCLK
(selection of frequency is programmable, see table 2)
t_WMH
t_WML
t_RM
t_{F M}
t_HBM
t_WFL
Period of MCLK High (measured from V_IH to V_IH, see note 1)
Period of MCLK Low (measured from V_IL to V_IL, see note 1 )
Rise Time of MCLK (measured from V_IL or V_IH)
Fall Time of MCLK (measured from V_IH to V_IL)
Hold Time, BCLK Low to MCLK High (TS5070 only)
Period of FS_X or FS_R Low (Measured from V_IL to V_IL)
(*) MCLK period
Min.
80
80
50
1
Typ.
512
1.536
1.544
2.048
4.096
Max.
30
30
Unit
kHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
(*)
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