TS5070 Datasheet, PDF (11/32 Pages) STMicroelectronics – PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION

Alternatively, the internal time-slot assignment
counters and comparators can be used to access
any time-slot in a frame,using the framesync inputs
as marker pulses for the beginning of transmit and
receive time-slot 0. In this mode, a frame may con-
sist of up to 64 time-slots of 8 bits each. A time-slot
is assignedby a 2-byte instructionas shown in table
1 and 6. The last 6 bits of the second byte indicate
the selected time-slot from 0-63 using straight bi-
nary notation. A new assignment becomes active
on the second frame following the end of the Chip
Select for the second control byte. The ”EN” bit al-
lows the PCM inputs D_R0/1 or outputs D_X0/1 as ap-
propriate, to be enabled or disabled.
Time-Slot Assignment mode requires that the FSX
and FSR pulses must conformto the delayedtiming
format shown in figure 6.
PORT SELECTION
On the TS5070 only, an additional capability is
available : 2 Transmit serial PCM ports, DX0 and
DX1, and 2 receive serial PCM ports, DR0 and DR1,
are provided to enable two-way space switching to
be implemented. Port selections for transmit and
receive are made within the appropriate time-slot
Table 7: Byte 2 of Transmit Gain Instructions.
Bit Number
76543210
00000000
00000001
00000010
10111111
11111110
11111111
(*) State at power initialization
RECEIVE GAIN INSTRUCTION BYTE 2
The receive gain can be programmed in 0.1 dB
steps by writing to the Receive GainRegister as de-
fined in table 1 and 8. Note the following restriction
on output drive capability :
a) 0 dBm0 levels ≤ 8.1dBm at VFRO may be
driven into a load of ≥ 15 kΩ to GND,
b) 0 dBm0 levels ≤ 7.6dBm at VFRO may be
driven into a load of ≥ 600 Ω to GND,
c) 0 dBm levels ≤ 6.9dBm at VFRO may be driven
TS5070 - TS5071
assignmentinstruction using the ”PS” bit in the sec-
ond byte.
On the TS5071, only ports DX0 and DR0 are avail-
able, therefore the ”PS” bit MUST always be set to
0 for these devices.
Table 6 shows the format for the second byte of
both transmitand receive time-slot and port assign-
ment instructions.
TRANSMIT GAIN INSTRUCTION BYTE 2
The transmit gain can be programmed in 0.1 dB
steps by writing to the Transmit Gain Register as
defined in tables 1 and 7. This corresponds to a
range of 0 dBm0 levels at VFXI between 1.619
Vrms and 0.087 Vrms (equivalent to + 6.4 dBm to
– 19.0 dBm in 600 Ω).
To calculate the binary code for byte 2 of this in-
struction for any desired input 0 dBm0 level in
Vrms, take the nearest integer to the decimal
number given by :
200 X log10 (V/√6 ) + 191
and convert to the binary equivalent. Some exam-
ples are given in table 7.
0dBm0 Test Leve at VF_XI
In dBm (Into 600Ω)
In Vrms (approx.)
No Output
– 19
– 18.9
0.087
0.088
0
0.775
+6.3
1.60
+6.4
1.62
into a load of ≥ 300 Ω to GND.
To calculate the binary code for byte 2 of this in-
struction for any desired output 0 dBm0 level in
Vrms, take the nearest integer to the decimal num-
ber given by :
a
200 X log10 (V/√6 ) + 174
n
d convert to the binary equivalent. Some exam-
ples are given in table 8.
11/32