TS5070 Datasheet, PDF (4/32 Pages) STMicroelectronics – PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION

TS5070 - TS5071
PIN CONNECTIONS
PLCC28
TS5070FN
DIP20
TS5071N
POWER SUPPLY, CLOCK
Name
Pin
Type
TS5070
FN
TS5071
N
Function
Description
V_CC
S
27
19
Positive Power + 5 V ± 5 %
Supply
V_SS
S
3
3
Negative
–5V± 5%
Power Supply
GND
S
1
1
Ground
All analog and digital signals are referenced to this pin.
BCLK
I
16
12
Bit Clock
Bit clock input used to shift PCM data into and out of the
D_R and D_X pins. BCLK may vary from 64 kHz to 4.096
MHz in 8 kHz increments, and must be synchronous with
MCLK (TS5071 only).
MCLK I
17
12
Master Clock Master clock input used by the switched capacitor filters
and the encoder and decoder sequencing logic. Must be
512 kHz, 1. 536/1. 544 MHz,
2.048 MHz or 4.096 MHz and synchronous with BCLK.
BCLK and MCLK are wired together in the TS5071.
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