RM0321 Datasheet, PDF (86/584 Pages) STMicroelectronics – SPEAr320S address map and registers

Multiport DDR controller (MPMC)
RM0321
Table 81. Memory controller parameters (continued)
Parameter
Description
power_down [0]
priority_en [0]
pwrup_srefresh_exit [0]
When this parameter is set to 1'b1, the Memory Controller will complete
processing of the current burst for the current transaction (if any), issue
a pre-charge all command and then disable the clock enable signal to
the DRAM devices. Any subsequent commands in the command queue
will be suspended until this parameter is set to 1'b0.
1'b0 - Enable full power state.
1'b1 - Disable the clock enable and power down the Memory Controller.
Controls priority as a condition when using the placement logic to fill the
command queue.
1'b0 - Disabled
1'b1 - Enabled
Controls controller to exit power-down mode by executing a self-refresh
instead of the full memory initialization.
1'b0 - Disabled
1'b1 - Enabled
q_fullness [3:0]
Defines quantity of data that will be considered full for the command
queue.
rd2rd_turn [0]
Adds an additional clock between back-to-back READ operations to
different chip selects. The extra clock is required for mobile DDR
devices where:
tac_max > (period/2+tac_min)
Without this additional clock, the first READ may drive DQS out at
tac_max and the second READ may drive DQS out at tac_min,
resulting in a contention on the DQS line.
1'b0 - Disabled
1'b1 - Enabled
reduc [0]
Controls the width of the memory datapath. When enabled, the upper
half of the memory buses (DQ, DQS and DM) are unused and relevant
data only exists in the lower half of the buses. This parameter expands
the Memory Controller for use with memory devices of the configured
width or half of the configured width.
1'b0 - Standard operation using full memory bus.
1'b1 - Memory datapath width is half of the maximum size.
reg_dimm_enable [0]
Enables registered DIMM operations to control the address and
command pipeline of the Memory Controller.
1'b0 - Normal operation
1'b1 - Enable registered DIMM operation.
rtt_0 [1:0]
Defines the On-Die termination resistance for all DRAM devices. The
Memory Controller can not be set for different termination values for
each chip select.
2'b00 - Termination Disabled
2'b01 - 75 Ohm
2'b10 - 150 Ohm
2'b11 - Reserved
86/584
Doc ID 022642 Rev 3