RM0321 Datasheet, PDF (154/584 Pages) STMicroelectronics – SPEAr320S address map and registers

USB 2.0 Device port (UDC)
9
USB 2.0 Device port (UDC)
RM0321
9.1
Register summary
The 32-bit wide control and status registers (CSRs) of the UDC-AHB subsystem provide a
high degree of control, making the device both configurable and scalable. These CSRs can
be accessed at the base address 0xE110.0000.
The CSRs can be grouped in two basic categories:
● Global CSRs (listed in Table 152), which are specific to the UDC-AHB subsystem.
● Endpoint CSRs (listed in Table 150 and in Table 151), which are specific to a particular
endpoint within the UDC-AHB subsystem. Specifically, each endpoint supported by the
UDC-AHB subsystem is associated to a set of specific 32-bit CSRs for each direction
(in/out).
As explained by the memory map in Figure 1, these CSRs are mapped in the 0x0000 to
0x04FC offset address space (with respect to the base address above). Apart from these
device-level CSRs, the UDC itself contains other specific CSRs which are mapped in the
0x0500 to 0x07FC offset address space.
Moreover, the FIFOs are mapped at base address 0xE100_0800. Offset addresses from
0x0800 up to a 0x1800 host the data in the RxFIFO (Receive FIFO controller), which are
followed by the memory space allocated to TxFIFOs.
Table 150. In endpoint-specific CSRs summary
Endpoint Name
Offset
Type
Reset value
0
Control
0x0000
RW
32’h0
Status
Buffer size
0x0004
0x0008
RO
32’h0
RW
32’h0
Maximum packet size
0x000C
RW
32’h0
Reserved
0x0010
-
-
Data description pointer
0x0014
RW
32’h0
Reserved
Write confirmation
0x0018
0x001C
-
-
RW
-
1
As Endpoint 0
0x0020 - 0x003C As Endpoint 0
Reserved
0x0040 - 0x005C
3
As Endpoint 0
Reserved
0x0060 - 0x007C
0x0080 - 0x009C
As Endpoint 0
5
As Endpoint 0
0x00A0 - 0x00BC As Endpoint 0
Reserved
0x00C0 - 0x00DC
7
As Endpoint 0
0x00E0 - 0x00FC As Endpoint 0
Reserved
9
As Endpoint 0
0x0100 - 0x011C
0x0120 - 0x013C
As Endpoint 0
Reserved
0x0140 - 0x015C
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Doc ID 022642 Rev 3