RM0321 Datasheet, PDF (475/584 Pages) STMicroelectronics – SPEAr320S address map and registers

RM0321
System configuration registers (MISC)
Table 543. Powerdown_CFG_CTR register bit assignments
Powerdown_CFG_CTR Register
0x0E0
Bit
Name
Reset
Value
Description
[31:01] RFU
-
[00] wakeup_fiq_enb 1’h0
Reserved for future use (Write don’t care - Read return zeros)
Wakeup interrupt type (Firq/Irq) definition; this field selects the
interrupt type detected from processor-1 to restore the normal
operating frequency from the power down state (switch from
sleep to doze/low speed operating mode):
1’b0: Irq interrupt type: the peripheral interrupt requests lines
are also used as a wakeup source event increasing the overall
interrupt latency time.
1’b1: Firq interrupt type: single global interrupt request line
which ensure both fast recovery time from power down state
and the best peripheral interrupt response time since the
wakeup SW interrupt service routine is centralized.
The wakeup interrupt vector is defined in the processor-1
interrupt table line-15.⁽¹⁾
1. IRQ interrupt type should be masked before to enter in sleep mode,
COMPSSTL_1V8_CFG/DDR_2V5_COMPENSATION register
The COMPSSTL_1V8_CFG/DDR_2V5_COMPENSATION is R/W registers which configure
the internal SSTL compensation cells parameters.
Table 544. COMPSSTL_1V8_CFG/DDR_2V5_COMPENSATION register bit
assignments
COMPSSTL_1V8_CFG Register
0x0E4
Bit
[31]
[30:24]
[23]
[22:16]
[15:05]
[04]
[03]
Name
TQ
rasrc
RFU
nasrc
RFU
COMPOK
accurate
Reset Value Description
1’h0
7'h78
-
-
-
1’h0
1’h1
It enables IDDq mode.
Writing code compensation parameter: field sampled from
the compensation macro-cell during Read operating mode
command (ref. Compensation cell operating mode table).
Reserved for future use (Write don’t care - Read return zeros)
Read code compensation parameter (RO); this field is
qualified from ‘sts_ok’ active high.
Reserved for future use (Write don’t care - Read return
zeros).
Valid code compensation (RO); field actives high in normal
mode when the measured code is available on the
compensation bus nasrc.
Compensation cell internal/external reference resistance
definition:
1’b0: Internal reference resistor
1’b1: External reference resistor: used to improve the
accuracy of compensation code value.
Doc ID 022642 Rev 3
475/584