RM0321 Datasheet, PDF (508/584 Pages) STMicroelectronics – SPEAr320S address map and registers

RAS configuration (RASCFG)
RM0321
[14] u_CAN_MEM_CLK_S: CAN0 Memory clock select
0: Inverted PCLK is directed to memory
1: PCLK is directed to memory
[13] l_CAN_MEM_CLK_S: CAN1 Memory clock select
0: Inverted PCLK is directed to memory
1: PCLK is directed to memory
[9] clcd_CLFP_sel: CLFP_selection
0: CLFP output as frame pulse only
1: CLFP output as ANDed version of frame pulse and line synchronization pulse
[8] AudioClk_sel: audio_over_samp_clk select
0: PLL2_CLKOUT
1: RAS_CLK_SYNT3
[7] Touchscreen_en: Touchscreen Enable
0: Disabled
1: Enabled
[6] UARTCLK_sel: UARTCLK select
0: RAS_CLK_SYNT2
1: PCLK
[5] RMII_MDIO_sel: RMII_MDIO select
0: MDIO signals are routed from RMII1
1: MDIO signals are routed from RMII2
[4] RMII2_endian: RMII2 DMA endianness
0: Little endian
1: Big endian
[3] RMII1_endian: RMII1 DMA endianness
0: Little endian
1: Big endian
[2:0] Mode_sel: Selects different modes as follows:
000: HMI Automation mode
001: MII automation networking mode
010: Expanded automation mode
011: Printer mode
Rest: Reserved
29.2.6 RASCFG touchscreen duration register
Touchscreen_Dur
Touchscreen Duration
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Touchscreen_dur
R/W
Address:
SP320S_RAS_REGsBaseAddress + 0x14
Type:
R/W
Reset:
0x0
Description:
Touchscreen Duration
[31:0] Touchscreen_dur: Touchscreen Duration (number of HCLK cycles) for sampling inputs
508/584
Doc ID 022642 Rev 3