RM0321 Datasheet, PDF (1/584 Pages) STMicroelectronics – SPEAr320S address map and registers

RM0321
Reference manual
SPEAr320S address map and registers
Introduction
This document provides the address map and register descriptions for the SPEAr320S,
embedded MPU with ARM926 core. Additional reference information is documented in the
manual RM0319 SPEAr320S architecture and functionality.
IP groups
Table 1. SPEAr320S IP groups
IP group
Constituent IPs
Processors, &
busses
General device
resources
Memory
interfaces
ARM926EJ-S
Bus interconnection matrix
Vectored interrupt controller (VIC)
DMA controller (DMAC)
General purpose timers (GPT)
Real-time clock (RTC)
System controller (SYSCTR)
Watchdog timer (WDT)
Cryptographic co-processor (C3)
System configuration registers (MISC)
Multiport DDR controller (MPMC)
MMC-SD card/SDIO controller
Serial NOR Flash controller (SMI)
Parallel NAND Flash controller (FSMC)
External memory interface (EMI)
Graphics, video,
& audio
High-speed
connectivity
LCD display controller (CLCD)
JPEG codec accelerator (JPGC)
Fast Ethernet port (MII0)
Fast Ethernet ports (RMII0/RMII1/MII1)
USB 2.0 Host ports (UHC)
USB 2.0 Device port (UDC)
November 2012
Doc ID 022642 Rev 3
www.st.com
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