RM0321 Datasheet, PDF (119/584 Pages) STMicroelectronics – SPEAr320S address map and registers

RM0321
USB 2.0 Host ports (UHC)
Table 117. USBSTS register bit assignments (continued)
Bit
Name
Reset value Description
[05]
IAA
[04]
HSE
Interrupt on async advance.
This status bit indicates the assertion of that interrupt
source. System software can force the EHCI host
1‘h0
controller to issue an interrupt the next time the EHCI
host controller advances the asynchronous schedule
by setting the interrupt on async advance doorbell bit
(IAAD) in the USBCMD register.
Host system error.
This bit is set by the EHCI host controller when a
serious error occurs during a host system access
1‘h0
involving the EHCI host controller module.
When this error occurs, the EHCI host controller
clears the RS bit in the USBCMD register to prevent
further execution of the scheduled TDs⁽¹⁾.
[03]
FLR
[02]
PCD
Frame list rollover.
This bit is set by the EHCI host controller when the
frame list index (see FRINDEX register in rolls over
from its maximum value to 0.
The exact value at which the rollover occurs depends
1‘h0
on the frame list size. For example, if the frame list
size (as programmed in the Frame list size, FLS, field
of the USBCMD register) is 1024 (FLS is 2‘b00), the
frame index register rolls over every time
FRINDEX[13] toggles. Similarly, if the size is 512
(FLS is 2‘b01), the EHCI host controller sets the FLR
bit every time FRINDEX[12] toggles.
Port change detect.
This bit is set by the EHCI host controller when any
port for which the port owner bit is set to 1‘b0 (bit PO
in port status controls register) has a change bit
transition from a 1‘b0 to a 1‘b1 or a force port resume
1‘h0
bit transition from a ‘b0 to a ‘b1 as a result of a J-K
transition detected on a suspended port.
This bit will also be set as a result of the connect
status change being set to 1‘b1 after system software
has relinquished ownership of a connected port by
writing a 1‘b1 to a port's port owner (PO) bit.
Doc ID 022642 Rev 3
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