RM0321 Datasheet, PDF (133/584 Pages) STMicroelectronics – SPEAr320S address map and registers

RM0321
USB 2.0 Host ports (UHC)
Table 129. HcControl register bit assignments (continued)
Read/Write
Bits Name Reset
Description
HCD HC
BulkListEnable
This bit is set to enable the processing of the Bulk list in
the next Frame. If cleared by HCD, processing of the Bulk
list does not occur after the next SOF. HC checks this bit
[05]
BLE 0b
R/W R
whenever it determines to process the list. When disabled,
HCD may modify the list. If HcBulkCurrentED is pointing
to an ED to be removed, HCD must advance the pointer
by updating HcBulkCurrentED before re-enabling
processing of the list.
ControlListEnable
This bit is set to enable the processing of the Control list in
the next Frame. If cleared by HCD, processing of the
Control list does not occur after the next SOF. HC must
[04]
CLE 0b
R/W R
check this bit whenever it determines to process the list.
When disabled, HCD may modify the list. If
HcControlCurrentED is pointing to an ED to be removed,
HCD must advance the pointer by updating
HcControlCurrentED before re-enabling processing of the
list.
[03]
IE
IsochronousEnable
This bit is used by HCD to enable/disable processing of
isochronous EDs. While processing the periodic list in a
Frame, HC checks the status of this bit when it finds an
0b
R/W R
Isochronous ED (F=1). If set (enabled), HC continues
processing the EDs. If cleared (disabled), HC halts
processing of the periodic list (which now contains only
isochronous EDs) and begins processing the Bulk/Control
lists. Setting this bit is guaranteed to take effect in the next
Frame (not the current Frame).
Doc ID 022642 Rev 3
133/584