ST92F124XX Datasheet, PDF (369/523 Pages) STMicroelectronics – In-Application Programming

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2
On-chip peripherals
Figure 149. J1850 received symbol timing
VPWO
Case 1 VPWI
VPW Decoder
VPWO
TX2
Case 2
VPWI
VPW Decoder
VPWO
TX2
Case 3
VPWI
VPW Decoder
178 µs
178 µs
178 µs
0 14
-6 8 22
200 214
192 208 222
Use of symbol and bit synchronization is an integral part of the J1850 bus scheme.
Therefore, tight coupling of the encoder and decoder functions is required to maintain
synchronization during transmits. Transmitted symbols and bits are initiated by the encoder
and are timed through the decoder to realize synchronization. Figure 149 exemplifies
synchronization with 3 examples for an SOF symbol and JDLY[4:0] = 01110b.
Case 1 shows a single transmitter arbitrating for the bus. The VPWO pin is asserted, and
14µs later the bus transitions to an active state. The 14µs delay is due to the nominal delay
through the external transceiver chip. The signal is echoed back to the transceiver through
the VPWI pin, and proceeds through the digital filter. The digital filter has a loop delay of 8
clock cycles with the signal finally presented to the decoder 22 µs after the VPWO pin was
asserted. The decoder waits 178 µs before issuing a signal to the encoder signifying the end
of the symbol. The VPWO pin is de-asserted producing the nominal SOF bit timing (22 µs +
178µs = 200 µs).
Case 2 shows a condition where 2 transmitters attempt to arbitrate for the bus at nearly the
same time with a second transmitter, TX2, beginning slightly earlier than the VPWO pin.
Since the JBLPD always times symbols from its receiver perspective, 178µs after the
decoder sees the rising edge it issues a signal to the encoder to signify the end of the SOF.
Nominal SOF timings are maintained and the JBLPD re-synchronizes to TX2.
Case 3 again shows an example of 2 transmitters attempting to arbitrate for the bus at
nearly the same time with the VPWO pin starting earlier than TX2. In this case TX2 is
required to re-synchronize to VPWO.
Doc ID 8848 Rev 7
369/523