ST92F124XX Datasheet, PDF (193/523 Pages) STMicroelectronics – In-Application Programming

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2
External memory interface (EXTMI)
EXTERNAL MEMORY REGISTER 2 (EMR2)
R246 - Read/Write
Register Page: 21
Reset value: 0001 1111 (1Fh)
7
-
ENCSR DPRREM
MEMSEL
LAS1
LAS0
UAS1
0
UAS0
Bit 7 = Reserved.
Bit 6 = ENCSR: Enable Code Segment Register.
This bit affects the ST9 CPU behavior whenever an interrupt request is issued.
0: The CPU works in original ST9 compatibility mode concerning stack frame during
interrupts. For the duration of the interrupt service routine, ISR is used instead of CSR, and
the interrupt stack frame is identical to that of the original ST9: only the PC and Flags are
pushed. This avoids saving the CSR on the stack in the event of an interrupt, thus ensuring
a faster interrupt response time. The drawback is that it is not possible for an interrupt
service routine to perform inter-segment calls or jumps: these instructions would update the
CSR, which, in this case, is not used (ISR is used instead). The code segment size for all
interrupt service routines is thus limited to 64K bytes.
1: If ENCSR is set, ISR is only used to point to the interrupt vector table and to initialize the
CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack
together with the PC and flags, and CSR is then loaded with the contents of ISR. In this
case, iret will also restore CSR from the stack. This approach allows interrupt service
routines to access the entire 4Mbytes of address space; the drawback is that the interrupt
response time is slightly increased, because of the need to also save CSR on the stack. Full
compatibility with the original ST9 is lost in this case, because the interrupt stack frame is
different; this difference, however, should not affect the vast majority of programs.
Bit 5 = DPRREM: Data Page Registers remapping
0: The locations of the four MMU (Memory Management Unit) Data Page Registers (DPR0,
DPR1, DPR2 and DPR3) are in page 21.
1: The four MMU Data Page Registers are swapped with that of the Data Registers of ports
0-3.
Refer to Figure 73.
Bit 4 = MEMSEL: Memory Selection.
Warning: Must be kept at 1.
Bit 3:2 = LAS[1:0]: Lower memory address strobe stretch.
These two bits contain the number of wait cycles (from 0 to 3) to add to the System Clock to
stretch AS during external lower memory block accesses (A21=”0”). The reset value is 3.
Doc ID 8848 Rev 7
193/523