ST92F124XX Datasheet, PDF (226/523 Pages) STMicroelectronics – In-Application Programming

On-chip peripherals
ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2
Figure 96. Output compare block diagram
16 BIT FREE RUNNING
COUNTER
16-bit
OUTPUT COMPARE
CIRCUIT
OC1E OC2E
OCIE
16-bit
OC1R
16-bit
OC2R
OCF1
CC1 CC0
(Control Register 2) CR2
(Control Register 1) CR1
OLVL2
OLVL1
OCF2 0
0
0
(Status Register) SR
Latch
1
Latch
2
OCMP1
OCMP2
Figure 97. Output compare timing diagram, internal clock divided by 2
INTCLK
TIMER CLOCK
COUNTER ^{FFFC FFFD FFFD FFFE} FFFF ⁰⁰⁰⁰
OUTPUT COMPARE REGISTER CPU writes FFFF
FFFF
COMPARE REGISTER LATCH
OCFi AND OCMPi PIN (OLVLi=1)
Forced compare mode
In this section i may represent 1 or 2.
The following bits of the CR1 register are used:
FOLV2
FOLV1
OLVL2
OLVL1
When the FOLV1 bit is set, the OLVL1 bit is copied to the OCMP1 pin if PWM and OPM are
both cleared.
When the FOLV2 bit is set, the OLVL2 bit is copied to the OCMP2 pin.
The OLVLi bit has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE
bit=1).
Notes:
● The OCFi bit is not set when FOLVi is set, and thus no interrupt request is generated.
● The OCFi bit can be set if OCiR = Counter and an interrupt can be generated if
enabled. This can be avoided by writing in the OCiHR register. The output compare
function is inhibited till OCiLR is also written.
● The Input Capture function works in Forced compare mode. To disable it, read the
ICiHR register. Input capture will be inhibited till ICiLR is read.
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Doc ID 8848 Rev 7