ST92F124XX Datasheet, PDF (347/523 Pages) STMicroelectronics – In-Application Programming

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2
On-chip peripherals
0: No event
1: One of the following events has occurred:
Byte received or to be transmitted
(I2CSR1.BTF and I2CSR1.EVF flags = 1)
Address matched in Slave mode while
I2CCR.ACK=1
(I2CSR1.ADSL and I2CSR1.EVF flags = 1)
Start condition generated
(I2CSR1.SB and I2CSR1.EVF flags = 1)
No acknowledge received after byte transmission
(I2CSR2.AF and I2CSR1.EVF flags = 1)
Stop detected in Slave mode
(I2CSR2.STOPF and I2CSR1.EVF flags = 1)
Arbitration lost in Master mode
(I2CSR2.ARLO and I2CSR1.EVF flags = 1)
Bus error, Start or Stop condition detected during data transfer
(I2CSR2.BERR and I2CSR1.EVF flags = 1)
Master has sent header byte
(I2CSR1.ADD10 and I2CSR1.EVF flags = 1)
Address byte successfully transmitted in Master mode.
(I2CSR1.EVF = 1 and I2CSR2.ADDTX=1)
Bit 6 = ADD10 10-bit addressing in Master mode.
This bit is set when the master has sent the first byte in 10-bit address mode. An interrupt is
generated if ITE=1.
It is cleared by software reading I2CSR1 register followed by a write in the I2CDR register of
the second address byte. It is also cleared by hardware when peripheral is disabled
(I2CCR.PE=0)
or when the STOPF bit is set.
0: No ADD10 event occurred.
1: Master has sent first address byte (header).
Bit 5 = TRA Transmitter/ Receiver.
When BTF flag of this register is set and also TRA=1, then a data byte has to be transmitted.
It is cleared automatically when BTF is cleared. It is also cleared by hardware after the
STOPF flag of I2CSR2 register is set, loss of bus arbitration (ARLO flag of I2CSR2 register
is set) or when the interface is disabled (I2CCR.PE=0).
0: A data byte is received (if I2CSR1.BTF=1)
1: A data byte can be transmitted (if I2CSR1.BTF=1)
Bit 4 = BUSY Bus Busy.
It indicates a communication in progress on the bus. The detection of the communications is
always active (even if the peripheral is disabled).
This bit is set by hardware on detection of a Start condition and cleared by hardware on
Doc ID 8848 Rev 7
347/523