ST92F124XX Datasheet, PDF (320/523 Pages) STMicroelectronics – In-Application Programming

On-chip peripherals
ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2
Procedure
● Define the serial clock baud rate by setting/resetting the DIV2 bit of SPPR register, by
writing a prescaler value in the SPPR register and programming the SPR0 & SPR1 bits
in the SPCR register.
● Select the CPOL and CPHA bits to define one of the four relationships between the
data transfer and the serial clock (see Figure 137).
● The SS pin must be connected to a high level signal during the complete byte transmit
sequence.
● The MSTR and SPOE bits must be set (they remain set only if the SS pin is connected
to a high level signal).
In this configuration the MOSI pin is a data output and the MISO pin is a data input.
Transmit Sequence
The transmit sequence begins when a byte is written the SPDR register.
The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a
write cycle and then shifted out serially to the MOSI pin most significant bit first.
Note:
When data transfer is complete:
● The SPIF bit is set by hardware
● An interrupt is generated if the SPIS and SPIE bits are set.
During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift
register is moved to a buffer. When the SPDR register is read, the SPI peripheral returns this
buffered value.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SPSR register while the SPIF bit is set
2. A read of the SPDR register.
While the SPIF bit is set, all writes to the SPDR register are inhibited until the SPSR register
is read.
Slave configuration
In slave configuration, the serial clock is received on the SCK pin from the master device.
The value of the SPPR register and SPR0 & SPR1 bits in the SPCR is not used for the data
transfer.
Procedure
● For correct data transfer, the slave device must be in the same timing mode as the
master device (CPOL and CPHA bits). See Figure 137.
● The SS pin must be connected to a low level signal during the complete byte transmit
sequence.
● Clear the MSTR bit and set the SPOE bit to assign the pins to alternate function.
In this configuration the MOSI pin is a data input and the MISO pin is a data output.
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Doc ID 8848 Rev 7