ST92F124XX Datasheet, PDF (350/523 Pages) STMicroelectronics – In-Application Programming

On-chip peripherals
ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2
Note:
Bit 2 = ARLO Arbitration Lost.
This bit is set by hardware when the interface (in master mode) loses the arbitration of the
bus to another master. An interrupt is generated if ITE=1.
It is cleared by software reading I2CSR2 register or by hardware when the interface is
disabled (I2CCR.PE=0).
After an ARLO event the interface switches back automatically to Slave mode (M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Bit 1 = BERR Bus Error.
This bit is set by hardware when the interface detects a Start or Stop condition during a byte
transfer. An interrupt is generated if ITE=1.
It is cleared by software reading I2CSR2 register or by hardware when the interface is
disabled (I2CCR.PE=0).
The SCL line is not held low while BERR=1.
If a misplaced start condition is detected, also the ARLO flag is set; moreover, if a misplaced
stop condition is placed on the acknowledge SCL pulse, also the AF flag is set.
0: No Start or Stop condition detected during byte transfer
1: Start or Stop condition detected during byte transfer
Bit 0 = GCAL General Call address matched.
This bit is set by hardware after an address matches with the value stored in the I2CADR
register while ENGC=1. In the I2CADR the General Call address must be placed before
enabling the peripheral.
It is cleared by hardware after the detection of a Stop condition, or when the peripheral is
disabled (I2CCR.PE=0).
0: No match
1: General Call address matched.
I²C CLOCK CONTROL REGISTER (I2CCCR)
R243 - Read / Write
Register Page: 20 (I2C_0) or 22 (I2C_1)
Reset Value: 0000 0000 (00h)
7
0
FM/SM
CC6
CC5
CC4
CC3
CC2
CC1
CC0
Bit 7 = FM/SM Fast/Standard I²C mode.
This bit is used to select between fast and standard mode. See the description of the
following bits.
It is set and cleared by software. It is not cleared when the peripheral is disabled
(I2CCR.PE=0)
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Doc ID 8848 Rev 7