ST92F124XX Datasheet, PDF (343/523 Pages) STMicroelectronics – In-Application Programming

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2
On-chip peripherals
Note:
Ready to Transmit” interrupt sources. The same correspondence exists about the internal
priority between interrupts.
The I2CCR.ITE bit has no effect on the End Of Block interrupts.
Moreover, the I2CSR1.EVF flag is not set by the End Of Block interrupts.
DMA between peripheral and register file
If the DMA transaction is made between the peripheral and the Register File, one register is
required to hold the DMA Address and one to hold the DMA transaction counter.
These two registers must be located in the Register File:
● the DMA Address Register in the even addressed register,
● the DMA Transaction Counter in the following register (odd address).
They are pointed to by the DMA Transaction Counter Pointer Register (I2CRDC register in
receiving, I2CTDC register in transmitting) located in the peripheral register page.
In order to select the DMA transaction with the Register File, the control bit
I2CRDC.RF/MEM in receiving mode or I2CTDC.RF/MEM in transmitting mode must be set.
The transaction Counter Register must be initialized with the number of DMA transfers to
perform and will be decremented after each transaction.
The DMA Address Register must be initialized with the starting address of the DMA table in
the Register File, and it is increased after each transaction. These two registers must be
located between addresses 00h and DFh of the Register File.
When the DMA occurs between Peripheral and Register File, the I2CTDAP register (in
transmission) and the I2CRDAP one (in reception) are not used.
DMA between peripheral and memory space
If the DMA transaction is made between the peripheral and Memory, a register pair is
required to hold the DMA Address and another register pair to hold the DMA Transaction
counter. These two pairs of registers must be located in the Register File. The DMA Address
pair is pointed to by the DMA Address Pointer Register (I2CRDAP register in reception,
I2CTDAP register in transmission) located in the peripheral register page; the DMA
Transaction Counter pair is pointed to by the DMA Transaction Counter Pointer Register
(I2CRDC register in reception, I2CTDC register in transmission) located in the peripheral
register page.
In order to select the DMA transaction with the Memory Space, the control bit
I2CRDC.RF/MEM in receiving mode or I2CTDC.RF/MEM in transmitting mode must be
reset.
The Transaction Counter registers pair must be initialized with the number of DMA transfers
to perform and will be decremented after each transaction. The DMA Address register pair
must be initialized with the starting address of the DMA table in the Memory Space, and it is
increased after each transaction. These two register pairs must be located between
addresses 00h and DFh of the Register File.
DMA in master receive
To correctly manage the reception of the last byte when the DMA in Master Receive mode is
used, the following sequence of operations must be performed:
Doc ID 8848 Rev 7
343/523