TDA7580_07 Datasheet, PDF (30/39 Pages) STMicroelectronics – FM/AM digital IF sampling processor

Functional description
TDA7580
There are built in filters for field strength processing. In order to obtain the maximum
flexibility the field strength processing and noise cancellation, however, are implemented as
software inside the programming DSP, which has to provide control signals for the stages
softmute, stereoblend, and highcut.
8.5
Serial audio interface (SAI)
The two SAI modules have been embedded in such a way great flexibility is available in their
use.
The two modules are fully separate and they each have a receive and a transmit channel, as
well as they can be selected as either master or slave.
The bit clocks and left & right clocks are routed through the pins, so the audio interface can
be chosen to be adapted to a large variety of application.
One SAI transmit channel can have the asynchronous sample rate converter in front, thus
separate different audio rate domains.
Additional feature are:
● support of 16/24/32 bit word length
● programmable left/right clock polarity
● programmable rising/falling edge of the bit clock for data valid
● programmable data shift direction, MSB or LSB received / transmitted first
8.6
I²C interfaces
The inter integrated circuit bus is a single bidirectional two wire bus used for efficient inter IC
control. All I²C bus compatible devices incorporate an on-chip interface which allows them
communicate directly with each other via the I²C bus.
Every component hooked up to the I²C bus has its own unique address whether it is a CPU,
memory or some other complex function chip. Each of these chips can act as a receiver and
/or transmitter on its functionality.
Two pins are used to interface both I²C of the DSP and RDS, which have different internal
I²C address, thus reducing the on board pin interconnections.
8.7
Serial peripheral interfaces
The DSP and RDS can have this serial interface, alternative to the I²C one. DSP and RDS
SPI modules have separate pin for chip select.
The DSP SPI has a ten 24 bit words deep FIFO for both receive and transmit sections,
which reduces DSP processing overhead even at high data rate.
The serial interface is needed to exchange commands and data over the LAN. During an
SPI transfer, data is transmitted and received simultaneously. A serial clock line
synchronizes shifting and sampling of the information on the two serial data lines. A slave
select line allows individual selection of a slave SPI device.
When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit
character is simultaneously shifted in a second data pin. The central element in the SPI
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