TDA7580_07 Datasheet, PDF (26/39 Pages) STMicroelectronics – FM/AM digital IF sampling processor

Inter processor transport interface for antenna diversity
TDA7580
6
Inter processor transport interface for antenna
diversity
(T_j =-40°C to 125°C; V_DD =1.7V to 1.9V, V_DD3 = 3.15V to 3.45V) C_load. The values on the
table are consistent with a capacitance load on HS³I lines of 20pF
Figure 14. High speed synchronous serial interface - HS³I
Master Bit Clock
Master Data Out
Master Synch
M2 M3
256 cycles of 74.1MHz
Slave Data Out
S0 S1 S2 S3
Figure 15. HS³I clocking scheme
t_mbco
t_mbcs
Master Bit Clock
Master Data Out
Master Synch
Slave Data Out
t_mbcc
t_sdos
Note:
Table 20. HS³I timing table
Timing
Description
t_sclk
t_dtr
t_setup
t_hold
MBC clock cycle
MBC active edge to master data out valid
MBC active edge to master synch valid
Slave data out setup time
T_DSP = DSP master clock cycle time = 1/F_DSP
Min Typ Max Unit
107.95
4
4
6
107.97 ns
ns
ns
ns
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