TDA7580_07 Datasheet, PDF (20/39 Pages) STMicroelectronics – FM/AM digital IF sampling processor

SAI Interface
3
SAI Interface
TDA7580
Note:
Figure 5. SAI Timings
SDI0-1
LRCKR
SCKR
(RCKP=0)
Valid
Valid
t_lrs
t_dt
t_sdis
t_sckpl
t_lrh
t_sdih
t_sckph
t_sckr
Table 17.
SAI Timing table
(T_j =-40°C to 125°C; V_DD =1.7V to 1.9V, V_DD3 = 3.15V to 3.45V) C_load The
values on the table are consistent with a capacitance load on SAI lines of
160pF
Timing
Description
Min Typ Max Unit
t_sckr
t_dt
t_lrs
t_lrh
t_sdis
t_sdih
t_sckph
t_sckpl
Clock Cycle
SCKR active edge to data out valid
LRCK setup time
LRCK hold time
SDI setup time
SDI hold time
SCK high time
SCK low time
302
976 ns
48
65
ns
25
ns
25
ns
65
ns
65
ns
146
ns
146
ns
T_DSP = DSP master clock cycle time = 1/F_DSP
Figure 6. SAI protocol (when: RLRS=0; RREL=0; RCKP=1; RDIR=0)
LRCKR
SCKR
LEFT
RIGHT
SDI0-1
LSB(n-1)
MSB(n)
MSB-1(n)
MSB-2(n)
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