TDA7580_07 Datasheet, PDF (13/39 Pages) STMicroelectronics – FM/AM digital IF sampling processor

TDA7580
Block diagram and electrical specifications
Table 5. Pin description (continued)
N°
Name
Type
Description
Notes
53 GNDH
54 VDDH
55 DBCK1
56 DBIN1
57 DBRQ1
58 DBOUT1
59 VDD
60 GND
61 VDDISO
62 GNDH
63 VDDH
64 VDDSD
G
3.3V IO ring power ground (debug
interface, GPIO)
P
3.3V IO ring power supply (Debug
interface, GPIO)
DSP1 debug port clock (DBCK1) if HS³I DSP1 GPIO9. 5V
B
master mode, else high speed
synchronous serial interface (HS³I)
tolerant. With internal
pull down, on at reset
channel3 data
[PP]
DSP1 GPIO or DSP1 debug port data in ^{DSP1 GPIO11}
B
(DBIN1) if HS³I master mode, else high 5V tolerant
speed synchronous serial interface (HS³I) _{With internal pull down,}
channel2 data i
on at reset [PP]
B
DSP1 GPIO or DSP1 debug port request
(DBRQ1) if HS³I master mode, else high
speed synchronous serial interface (HS³I)
channel1 data
5V tolerant. With
internal pull up, on at
reset [PP]
DSP1 GPIO or DSP1 debug port data out ^{DSP1 GPIO10}
B
(DBOUT1) if HS³I master mode, else high 5V tolerant
speed synchronous serial interface (HS³I) _{With internal pull up, on}
clock
at reset [PP]
P Digital core power supply
1.8V
G Digital core power ground
P 3.3V N-isolation biasing supply
Clean 3.3V supply to be
star connected to
voltage regulator
G
3.3V IO ring power ground
(modulator digital section)
P
3.3V IO ring power supply
(modulator digital section)
P
3.3V IFADC modulator analogue power
supply
Clean power supply, to
be star connected to
3.3V voltage regulator
After
Reset
Input
Input
Input
Input
I/O Type
P: Power supply from voltage regulator
G: Power ground from voltage regulator
A: Analogue I/O
I: Digital input
O: Digital output
B: Bidirectional I/O
I/O Definition and status
Z: high impedance (input)
O: logic low output
X: undefined output
1: logic high output
Output PP: Push pull / OD: Open drain
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