TDA7580_07 Datasheet, PDF (27/39 Pages) STMicroelectronics – FM/AM digital IF sampling processor

TDA7580
7
I²C timing
Figure 16. DSP and RDS I²C BUS timings
I²C timing
Table 21. I²C BUS timing table
(T_j =-40°C to 125°C; V_DD =1.7V to 1.9V, V_DD3 = 3.15V to 3.45V)
Symbol
Parameter
Test
condition
Standard mode
I²C BUS
Min. Max.
Fast mode
I²C BUS
Unit
Min.
Max.
F_SCL
t_BUF
SCLl clock frequency
Bus free between a stop and start
condition
0
100
0
4800
–
1300
400 kHz
–
ns
Hold time (repeated) START condition.
t_HD:STA After this period, the first clock pulse is
generated
4800
–
600
–
ns
t_LOW
t_HIGH
t_SU:STA
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated start
condition
4800
–
1300
–
ns
4800
–
600
–
ns
4800
–
600
–
ns
t_HD:DAT DATA hold time
0
-
0
900
ns
t_R Rise time of both SDA and SCL signals Cb in pF
–
300 12+0.1C_b 300
ns
t_F Fall time of both SDA and SCL signals Cb in pF
–
300 12+0.1C_b 300
ns
t_SU;STO Set-up time for STOP condition
4800
–
600
–
ns
t_SU:DAT Data set-up time
250
–
250
–
ns
C_b Capacitive load for each bus line
10
400
10
400
pF
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