TDA7580_07 Datasheet, PDF (22/39 Pages) STMicroelectronics – FM/AM digital IF sampling processor

RDS SPI interface
4
RDS SPI interface
Figure 10. RDS SPI timings
SS
MISO
MOSI
SCL
(CPOL=0,CPHA=0)
Valid
t_dtr
t_setup
t_sssetup
t_sclkl
t_hold
t_sclkh
t_sclk
TDA7580
t_sshold t_ssw
Table 18.
Symbol
RDS SPI timing table
(T_j =-40°C to 125°C; V_DD =1.7V to 1.9V, V_DD3 = 3.15V to 3.45V) C_load The
values on the table are consistent with a capacitance load on RDS SPI lines of
80pF
Description
Min
Typ
Max Unit
Slave configured
t_sclk
t_dtr
t_setup
t_hold
t_sclkh
t_sclkl
t_sssetup
t_sshold
t_ssw
Clock cycle
Sclk edge to MISO valid
MOSI setup time
MOSI hold time
SCK high time width
SCK low time width
SS setup time
SS hold time
SS pulse width
1240
239
255
365
620
620
620
620
1240
ns
365
ns
ns
ns
ns
ns
ns
ns
ns
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