TDA7580_07 Datasheet, PDF (10/39 Pages) STMicroelectronics – FM/AM digital IF sampling processor

Block diagram and electrical specifications
TDA7580
Table 5. Pin description (continued)
N°
Name
Type
Description
Notes
After
Reset
7 GNDSD
G IFADC modulator analogue ground
Clean ground, to be star
connected to voltage
regulator ground
8 GNDOSC
G Oscillator ground
Clean ground, to be star
connected to voltage
regulator ground
9 XTI
I
High impedance oscillator input (quartz
connection) or clock input when in
Antenna Diversity slave mode
Maximum voltage swing
is VDD=3.3V
10 XTO
O
Low impedance oscillator output (quartz
connection)
11 VDDOSC
P Oscillator power supply
3.3V
12 VDDMTR
P
Tuner reference clock and AGC keying
DAC power supply
1.8V
13 CKREFP
B Tuner reference clock positive output.
FM 100kHz
AM_EU 18kHz
With internal pull-up, on
at reset [PP]
Output
14 CKREFN
B Tuner reference clock negative output.
FM 100kHz
AM_EU 18kHz
With internal pull-up, on
at reset [PP]
Output
15 AGCKEY
A DAC output for Tuner AGC keying
1.5kohm ±30% output
impedance. 1Vpp ±1%
output dynamic range
16 GNDMTR
G
Ground of the tuner reference clock buffer
and the AGC keying DAC
17 PROTSEL_SS
DSP0 GPIO for control serial interface
(low: SPI or high: I²C) selection at device ^{DSP0 GPIO0}
Bootstrap.
B
In SPI protocol mode, after boot
5V tolerant
With internal pull-up, on
Input
procedure, SPI slave select, otherwise _{at reset [PP]}
DSP0 GPIO0
18 SDA_MOSI
Control serial interface and RDS IO:
5V tolerant
B
- SPI mode: slave data in or master data
out for main SPI & RDS SPI data in
With internal pull-up, on
Input
- I²C mode: data for main I²C or RDS I²C ^{at reset [PP]}
19 MISO
B
SPI slave data out or master data in for
main SPI and RDS SPI data out
DSP0 GPIO1
5V tolerant. With
internal pull-up, on at
reset [PP]
Input
20 SCL_SCK
B
Bit clock for Control Serial Interface and
RDS
5V tolerant. With
internal pull-up, on at
reset [PP]
Input
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