STCOM Datasheet, PDF (24/58 Pages) STMicroelectronics – Powerline communication and application system-on-chip

Description
STCOM
At a startup the 24 MHz oscillator clock is selected. This source must be always present to
allow the STCOM starting correctly. 24 MHz can be provided by a quartz crystal or by any
other source. In this latter case, the clock must be provided through the MCLK_IN pin while
the MCLK_OUT pin must be tied to DGND. 32.768 KHz must be provided by a quartz
crystal.
APB peripherals can work up to 48 MHz. Each PCLK prescaler to the sub-systems should
be configured to respect this maximum frequency.
The general purpose ADC clock can run up to 33 MHz. The RTC core uses only the 32 KHz
external oscillator. The TRNG can work with the external 32 kHz or with the internal
cpu_hclk. If the internal clock is selected, the divisor should be configured to provide an
accurate 32 kHz clock in order to respect the requirements for a true random generation.
One master clock output line can be enabled. The MCO1 is multiplexed with one general
purpose I/O and can take one of the QFS outputs with a configurable prescaler.
1.8
Power management
The STCOM should be powered with, at least, two external supply voltages:
 3.3 V for I/Os, embedded Flash, QFS, DAC, OSC, ADC general purpose, 1.2 V
regulator
 8 - 18 V for line driver
The device needs also two more supply voltages that can be generated internally:
 1.2 V for digital cores and logic, embedded Flash, QFS and oscillator
 5 V for the PLC AFE
1.2 V and 5 V can be provided by two internal linear regulators connected respectively to
DVDD_1V2 and AVDD_5V pins and supplied respectively by DVDD_3V3_REG and PVCC
pins. A bypass mode is available for the 1.2 V regulator in case an external source is used.
The power-on reset (POR) is conditioned by the level of DVDD_3 V3_IO and DVDD_1V2: at
power on, the whole STCOM device is kept under reset until the two supply voltages are
above the respective turn-on thresholds named V(DVDD_3 V3_IO)_TH and
V(DVDD_1V2)_TH, while the device is turned off as soon as one of the voltages goes below
its turn-off thresholds, namely V(DVDD_3 V3_IO)_TL and V(DVDD_1V2)_TL.
An internal comparator checks the supply voltage on AVDD_5V_AFE as well, enabling the
use of the PLC AFE when the voltage is above V(AVDD_5V_AFE)_TH and disabling it when
the voltage goes below V(AVDD_5V_AFE)_TL.
Refer to Figure 5 and Figure 6 for the detailed power supply scheme.
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