STCOM Datasheet, PDF (16/58 Pages) STMicroelectronics – Powerline communication and application system-on-chip

Description
STCOM
1.3.5
1.3.6
1.3.7
Memory protection unit (MPU)
The MPU divides the memory map into up to 8 regions, and defines the location, size,
access permissions, and memory attributes of each region. It supports:
 Independent attribute settings for each region
 Overlapping regions
 Export of memory attributes to the system.
 Background region
When memory regions overlap, memory access is affected by the attributes of the region
with the highest number.
The background region has the same memory access attributes as the default memory
map, but is accessible from privileged software only.
The MPU is useful to isolate and protect different parts of the firmware by giving different
levels of access privileges. If a part of the firmware tries to access a memory location that is
prohibited by the MPU, the processor generates a fault. This causes a fault exception that
could be detected by the privileged firmware, which can take the appropriate action.
The MPU is optional and can be bypassed for applications that do not need it.
Debug and trace
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Embedded Trace Macrocell™ (ETM)
The ARM Embedded Trace Macrocell provides greater visibility of the instruction and data
flow inside the Cortex™-M4 core by streaming compressed data at a very high rate from the
STCOM device through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is then connected to a host in order to record and then
format the information for displaying and analysis.
General purpose input/outputs (GPIOs)
The STCOM device has 11 GPIOs ports named from GPIO00 to GPIO10. Each port is able
to manage 8 pins, except the GPIO08 port that manages 6 pins. Each GPIO pin can be
individually configured by software as output (push-pull or open drain, with or without pull-up
or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral
alternate functions (with or without pull-up or pull-down). Each GPIO pin can also generate
interrupt depending on a level (low and high), or a transactional value of the pin (rising or
falling edge).
External interrupt
Each GPIOs port can generate interrupts. For each port one interrupt line is dedicated. The
pins of one port share the same interrupt line.
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