STCOM Datasheet, PDF (11/58 Pages) STMicroelectronics – Powerline communication and application system-on-chip

STCOM
Description
Table 1. Cortex™-M4F core configuration
Component
Presence
Comment
JTAG
Yes
Full-featured debug access port (DAP), SWJ-DP and AHB access port
ETM
Yes
ITM
Yes
TPIU
Yes
FPB
Yes
Embedded Trace Macrocell present
Instrumentation Trace Macrocell
Trace port unit interface present
Flash patch breakpoint
DWT
Yes
Data watchpoint and trace
DEBUG level
N/A
IRQ
N/A
Priority level
N/A
MPU
Yes
Full debug with data matching for watchpoint generation
80 IRQ source
Set to 5:32 levels
Memory protection unit present. 8 regions implemented
FPU
Yes
BB
Yes
RESET_ALL_REGS Yes
CLKGATE
Yes
Floating point unit present (single precision)
Bit banding region present
Reset all synchronous state
Possibility to minimize dynamic power dissipation by clock gating
WIC
Yes
10 lines: NMI, WWDG, RTC, GPIOs, IPC, DMA, GPT0, SPI0 and USART0
1.3.2
1.3.3
Floating point unit (FPU)
The FPU fully supports single precision add, subtract, multiply, divide, multiply and
accumulate, and square root operations. It also provides conversions between the fixed
point and floating point data formats, and floating point constant instructions.
The FPU provides floating point operations that are compliant with the NSI/IEEE Std 754-
2008 A, IEEE Standard for Binary Floating-point Arithmetic^©, referred to as the IEEE 754
Standard.
The FPU contains 32 single precision extension registers, which can also be accessible as
16 double word registers for load, store, and move operations.
Nested vectored interrupt controller (NVIC)
The STCOM embeds a NVIC able to handle 80 maskable interrupts. The software priority
level is configurable in the range of 0 - 31 for each interrupt. A higher level corresponds to
a lower priority, so the level 0 is the highest interrupt priority. In case two or more interrupt
lines share the same software priority level, the hardware priority level, which is described in
Table 2, is used.
DocID028515 Rev 1
11/58
58