STCOM Datasheet, PDF (14/58 Pages) STMicroelectronics – Powerline communication and application system-on-chip

Description
STCOM
Position Priority
60
67
61
68
62
69
63
70
64
71
65
72
66
73
67
74
68
75
69
76
70
77
71
78
72
79
73
80
74
81
75
82
76
83
77
84
78
85
79
86
Table 2. Interrupt definition and position (continued)
Acronym
Description
GPIO02
GPIO02 global interrupt
GPIO03
GPIO03 global interrupt
GPIO04
GPIO04 global interrupt
GPIO05
GPIO05 global interrupt
GPIO06
GPIO06 global interrupt
GPIO07
GPIO07 global interrupt
GPIO08
GPIO08 global interrupt
GPIO09
GPIO09 global interrupt
GPIO10
GPIO10 global interrupt
GPT4
GPT4 - global interrupt
GPT5
GPT5 - global interrupt
GPT6
GPT6 - global interrupt
GPT7
GPT7 - global interrupt
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
1.3.4
DMA controller (DMA)
The STCOM embeds 1 general purpose dual port DMA controller with 8 channels. It is able
to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers.
It features dedicated FIFOs for APB/AHB peripherals, a supports burst transfer and is
designed to provide the maximum peripheral bandwidth (AHB/APB).
The DMA controller supports circular buffer management, so that no specific code is needed
when the controller reaches the end of the buffer. It also has a double buffering feature,
which automates the use and switching of two memory buffers without requiring any special
code.
Each channel is connected to dedicated hardware DMA requests, with support for
a software trigger on each stream. Configuration is made by software and transfer sizes
between source and destination are independent.
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