S29NS-J Datasheet, PDF (70/85 Pages) SPANSION – 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories

Data Sheet
AC Characteristics
AVD# low with clock
present enables
burst read mode
device is programmable from 2 to 7 total cycles
during initial access (here, programmable wait state
function is set to 04h; 6 cycles total)
2 additional
wait states if
address is
at boundary
CLK
AVD#
RDY
A/DQ15–
A/DQ0
Address
High-Z
D0
Amax–A16
Address
t_OE
OE#
D1
D2
Note: Devices should be programmed with wait states as discussed in the “Programmable Wait State” section on page 16.
Figure 22. Initial Access at 3Eh with Address Boundary Latency
CE#
A/DQ
Addresses
AVD#
CLK
t_AVDSM
t_IACC
D0
D1
D2
OE#
Hi-Z
RDY
Note: If t_AVDSM > 1 CLK cycle, wait state usage is reduced. Figure shows 40 MHz clock, handshaking enabled. Wait state usage is
4 clock cycles instead of 5. Note that t_AVDSM must be less than 76 µs for burst operation to begin.
Figure 23. Example of Extended Valid Address Reducing Wait State Usage
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S29NS-J
S29NS-J_00_A10 March 22, 2006