S29NS-J Datasheet, PDF (52/85 Pages) SPANSION – 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories

Data Sheet
START
Read Byte
(DQ0-DQ7)
Address = VA
Read Byte
(DQ0-DQ7)
Address = VA
DQ6 = Toggle?
No
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ 0-DQ7)
Adrdess = VA
DQ6 = Toggle?
No
Yes
FAIL
PASS
Note: The system should recheck the toggle bit even if DQ5 =
“1” because the toggle bit may stop toggling as DQ5 changes
to “1.” See the subsections on DQ6 and DQ2 for more
information.
Figure 4. Toggle Bit Algorithm
whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sec-
tors are selected for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 20 to compare outputs for DQ2 and DQ6.
See the following for additional information: (toggle bit flowchart), DQ6: Toggle Bit I (descrip-
tion), 19 (toggle bit timing diagram), and Table 19 (compares DQ2 and DQ6).
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S29NS-J
S29NS-J_00_A10 March 22, 2006