S29NS-J Datasheet, PDF (48/85 Pages) SPANSION – 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories

Data Sheet
Command Sequence
(Notes)
Asynchronous Read (7)
Reset (8)
Manufacturer ID
Device ID
Sector Lock Verify (13)
Revision ID (14)
Mode Entry
Program (15)
Table 18. Command Definitions
First
Second
Addr Data Addr Data
1 RA RD
1 XXX F0
Bus Cycles (Notes 1–6)
Third
Fourth
Addr Data Addr
Data
Fifth
Addr Data
Sixth
Addr
Data
4 555 AA 2AA 55 (BA)555 90 (BA)X00 0001
6 555 AA 2AA 55 (BA)555 90 (BA)X01 (10) (BA)X0E (11) (BA) X0F
4 555 AA 2AA 55 (SA)555 90 (SA)X02 (13)
(12)
4 555 AA 2AA 55 (BA)555 90 (BA)X03 (14)
3 555 AA 2AA 55
555
20
2 XXX A0 PA PD
Reset (16)
2 BA 90 XXX 00
Program
4 555 AA 2AA 55
555
A0
PA
PD
Chip Erase
6 555 AA 2AA 55
555
80
555
AA
2AA
55
555
10
Sector Erase
6 555 AA 2AA 55
555
80
555
AA
2AA
55
SA
30
Erase Suspend (17)
1 BA B0
Erase Resume (18)
1 BA 30
Sector Lock/Unlock
3 XXX 60 XXX 60
SLA
60
Set Config. Register (19)
3 555 AA 2AA 55 (CR)555 C0
CFI Query (20)
1 55 98
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
5. Unless otherwise noted, address bits A_max–A12 are don’t cares.
6. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
7. No unlock or command cycles required when bank is reading
array data.
8. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information).
9. The fourth cycle of the autoselect command sequence is a read
cycle. The system must read device IDs across the 4th, 5th, and
6th cycles, The system must provide the bank address. See the
Autoselect Command Sequence section for more information.
10. For S29NS128J, the data is 007Eh. For S29NS064J, the data is
277Eh. For S29NS032J, the data is 2A7Eh. For S29NS016J, the
data is 297Eh.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A_max–A13 uniquely select any sector.
BA = Address of the bank (A22–A21 for S29NS128J, A21–A20 for
S29NS064J, A20–A19 for S29NS032J, A19–A18 for S29NS016J) that
is being switched to autoselect mode, is in bypass mode, or is being
erased.
SLA = Address of the sector to be locked. Set sector address (SA) and
either A6 = 1 for unlocked or A6 = 0 for locked.
CR = Configuration Register set by address bits A17–A12.
11. For S29NS128J, the data is 0016h. For S29NS064J, the data is
2702h, for S29NS032J, the data is 2A24h, for S29NS016J, the
data is 2915h.
12. For S29NS128J, the data is 0000h, for S29NS064J, the data is
2700h, for S29NS032J, the data is 2A00h for S29NS016J, the
data is 2900h.
13. The data is 0000h for an unlocked sector and 0001h for a locked
sector.
14. The data is TBD, based on Nokia spec.
15. The Unlock Bypass command sequence is required prior to this
command sequence.
16. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
17. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
18. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
19. The addresses in the third cycle must contain, on A17–A12, the
additional wait counts to be set. See “Set Configuration Register
Command Sequence”.
20. Command is valid when device is ready to read array data or
when device is in autoselect mode.
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S29NS-J
S29NS-J_00_A10 March 22, 2006