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| S29NS-J Datasheet, PDF (69/85 Pages) SPANSION – 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, Burst Mode Flash Memories | |||
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Data Sheet
AC Characteristics
Address wraps back to beginning of address group.
Initial Access
CLK
Address (hex)
39
39
3A
3B
3C
3D
3E
3F
38
A/DQ15â
A/DQ0
D0
D1
D2
D3
D4
D5
D6
D7
VIH
AVD#
VIL
OE# VIH
VIL
CE#
VIL
(stays low)
Note: 8-word linear burst mode shown. 16- and 32-word linear burst read modes behave similarly. D0 represents the first
word of the linear burst.
Figure 20. 8-, 16-, and 32-Word Linear Burst Address Wrap Around
Address boundary occurs every 64 words, beginning at address
00003Fh: 00007Fh, 0000BFh, etc. Address 000000h is also a boundary crossing.
C60
C61
C62 C63
CLK
Address (hex)
3C
3D
3E
3F
VIH
AVD# (stays high)
VIL
RDY
C63
C63
C64
C65
C66
C67
40
41
42
43
tRACC
latency
A/DQ15â
A/DQ0
D60
D61
D62
D63
D64
D65
OE#,
VIH
(stays low)
CE# VIL
Note: Cxx indicates the clock that triggers data Dxx on the outputs; for example, C60 triggers D60.
Figure 21. Latency with Boundary Crossing
D66 D67
March 22, 2006 S29NS-J_00_A10
S29NS-J
65
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